Principal Engineer – SoC Physical Design or Chip-Level Expert

Aion Silicon Ltd; Barcelona; On-site; EUR 150,000 - 190,000; Full time

Job summary

Aion Silicon Ltd seeks a seasoned Principal Engineer for SoC Physical Design to lead complex ASIC/SoC implementations from architecture to tape-out. You will drive full-chip physical design, floorplanning, power/clock planning, PMU strategies, and signoff, collaborating across Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

Ideal candidates bring 15+ years of ASIC/SoC PD experience, a proven tape-out record, and deep expertise in 22nm and below nodes,

Qualifications

• 15+ years of ASIC/SoC Physical Design experience.
• Proven tape-out track record for SoC/ASIC projects.
• Strong understanding of floorplanning, clock & power distribution, global signal planning, I/O planning and hard IP integration.
• Experience with multi-voltage and multi-clock domain SoCs, ESD strategies, mixed-signal integration, and package-aware design.

Responsibilities

• Lead full-chip physical design from architecture through tape-out.
• Drive methodology, signoff, and execution across teams (Architecture, RTL, Verification, DFT, STA, Packaging).
• Define milestones, track progress, manage dependencies and ensure on-time tape-out.
• Coordinate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to meet goals.
• Troubleshoot design, flow, and methodology issues; mentor engineers and improve flows.

Skills

Leadership

SoC Integration

Tape-outs

Cross-functional work

Mentoring

Education

B.Tech / M.Tech in Electrical Engineering or related

Tools

Calibre

IC Validator (ICV)

Pegasus

RedHawk

Voltus

PrimePower

TCL

Perl

Python

Job description

We are seeking a highly motivated and experienced Principal Engineer - SoC Physical Design or Chip-Level Expert to lead the implementation of complex ASIC/SoC designs from architecture definition through successful tape-out. The ideal candidate will have deep expertise in full-chip physical design, SoC integration, advanced-node implementation, and cross-functional technical leadership.

This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT, STA, Package, and Silicon Validation teams.

Key Responsibilities

Partner with Front-End and Architecture teams to understand chip architecture and drive physical design considerations early in the development cycle.

Lead full-chip physical implementation activities including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff.

Drive physical design methodologies, best-known methods (BKMs), checklists, and implementation guidelines across projects.

Serve as the technical focal point for physical design execution and coordinate activities across block, subsystem, and top-level implementation teams.

Define project milestones, track progress, manage dependencies, and drive execution to meet tape-out schedules.

Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to achieve project goals.

Drive closure of timing, congestion, power, IR drop, EM, signal integrity, and physical verification requirements.

Debug and resolve design, flow, and methodology issues, identifying scalable solutions and driving implementation.

Mentor engineers and contribute to the continuous improvement of design methodologies and automation flows.

Required / Preferred Qualifications

B.Tech / M.Tech in Electrical Engineering, Electronics, Computer Engineering, or related discipline.

15+ years of ASIC/SoC Physical Design experience.

Proven track record of multiple successful SoC/ASIC tape-outs.

Strong understanding of ASIC/SoC integration, including floorplanning, clock distribution, power distribution networks, global signal planning, I/O planning, and hard IP integration.

Experience addressing complex SoC challenges involving multiple voltage domains, multiple clock domains, ESD implementation strategies, mixed-signal integration, and package-aware design considerations.

Solid knowledge of hierarchical and top-down design methodologies, budgeting techniques, timing convergence, and physical convergence strategies for large-scale SoCs.

Experience integrating IPs from both internal and external vendors and driving physical implementation requirements throughout the design lifecycle.

Hands-on experience with large-scale SoCs exceeding >20M gates and operating at frequencies greater than 1GHz.

Strong understanding of physical design databases, data management, and implementation-signoff consistency.

Experience in advanced technology nodes including 22nm, 16nm, 7nm, 5nm, and below.

Strong leadership skills with the ability to drive execution across geographically distributed teams.

Experience leading or contributing to multiple successful full-chip SoC tape-outs with ownership of implementation, timing closure, power integrity, physical verification, and signoff.

Tools Required

Physical Verification: Calibre, IC Validator (ICV), Pegasus.

Power Integrity & Signoff: RedHawk, Voltus, PrimePower.

Scripting & Automation: TCL, Perl, Python, Shell scripting.