SoC Interconnect Senior Architect — Hybrid, Flexible Schedule

OPENCHIP & SOFTWARE TECHNOLOGIES; Barcelona; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Hybrid work environment

Flexible schedule

Competitive remuneration based on exp

Job summary

Openchip & Software Technologies S.L. is seeking a senior SoC Interconnect Architect to develop and verify state-of-the-art Memory Interface and Network-on-Chip IP cores.

You will work on advanced device architectures, provide design guidelines, and collaborate with SoC, verification and SW teams to enable successful interconnect deployments. The role demands extensive experience in IP/SoC design, SystemVerilog, and RISC-V, with a shared commitment to high-performance, low-power interconnects in

Qualifications

• 7+ years in IP/SoC design.
• Experience with SoC architectures.
• Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, APB.
• Knowledge of cache-coherent memory systems and interconnects.
• Familiarity with RISC-V architecture.
• Proficiency in SystemVerilog/Verilog, C/C++, Python.
• Experience with RTL design, verification and simulation.

Responsibilities

• Develop and verify Memory Interface and Network-on-Chip IP cores.
• Work on advanced device architectures, design definition, implementation, and verification.
• Develop design examples and simulation models with comprehensive documentation.
• Deliver RTL to the SoC team and support verification and silicon validation.

Skills

SoC IP design

Network-on-Chip

SystemVerilog

Verilog

C/C++

Python scripting

RISC-V

Job description

Openchip & Software Technologies S.L. is seeking a senior SoC Interconnect Architect to develop and verify state-of-the-art Memory Interface and Network-on-Chip IP cores.

You will work on advanced device architectures, provide design guidelines, and collaborate with SoC, verification and SW teams to enable successful interconnect deployments. The role demands extensive experience in IP/SoC design, SystemVerilog, and RISC-V, with a shared commitment to high-performance, low-power interconnects in