Senior Formal Verification Engineer

Openchip & Software Technologies; Barcelona; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Hybrid work model

Autonomy and ownership

European collaboration

Job summary

Openchip & Software Technologies S.L. is seeking a Senior Formal Verification Engineer to lead the formal verification strategy across our SoC platforms.

You will work with system architects to establish verification environments, write SystemVerilog assertions, and guide the use of formal methods to improve IP and chip-level verification efficiency. You will design verification methodologies, create multi-level test plans, analyze coverage, and participate in regression frameworks and project

Qualifications

• Master's degree in relevant field.
• Min 5 years of experience in Formal Verification.
• Deep understanding of formal verification concepts at SoC level.
• Significant contributions in formal verification.
• Experience with SystemVerilog and SV assertions.

Responsibilities

• Establish formal verification environment with system architects and design team.
• Guide use of formal verification to improve IP/SoC verification efficiency.
• Define Formal Verification Methodologies.
• Produce IP/subsystem/chip level test plans from design docs.
• Write and debug SystemVerilog assertions.
• Analyze coverage and address holes with design teams.
• Develop framework for regression runs and debugging failures.
• Support integration and test planning of designs at subsystem level.
• Iterate workflows with scripting/AI techniques to streamline processes.
• Participate in project reviews and provide guidance to teammates.

Skills

Formal verification

SystemVerilog

SV assertions

Scripting

Debugging

CPU/NoC/Memory

Education

Master's degree

Tools

Formal tools

SystemVerilog

Job description

The Role

As a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems.

Responsibilities

• Work closely with system architects and design team to establish formal verification environment and setting


• Guide the use of formal verification so that correct formal techniques are used appropriately to improve efficiency of IP and SoC level verification


• Contribute to define Formal Verification Methodologies


• Produce IP level, subsystem level and chip level test plans based on Design documents and interaction with design and architecture teams


• Write and debug System Verilog assertions


• Analyze coverage data and working with Design teams to address coverage holes


• Contribute to developing framework for running regressions and debugging regression failures


• Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level


• Scripting/Automation skills for improving workflows along with the usage of most advanced AI techniques


• Participate in project reviews


• Provide supervision/guidance to other team members

Required Qualifications

• Master's degree in relevant field


• Min 5 years of experience in relevant field of Formal Verification


• A deep understanding of formal verification, including applications, verification of algorithms, protocols, and application of formal verification at SoC level


• Made significant contributions in the use of formal verification and be able to guide formal verification development into new areas


• Formal tools, System Verilog, SV Assertions and Assumptions, Scripting skills


• Apps in formal tools (Low power, X-prop, Connectivity checking, Register Map Verification)


• Design debug, Deep bug hunting


• Design knowledge of CPU, NoC/Interconnect, Memory Controllers, Caches

Soft Skills

• Team player, able to work with multiple cultures both on site and remotely


• Autonomous and flexible is mandatory

What We Offer?

• The opportunity to build a cloud AI deployment platform that will power next generation AI systems.


• A collaborative, innovation-driven environment with significant autonomy and ownership.


• Hybrid work model with flexible scheduling.


• A chance to join one of Europe's most ambitious companies at the intersection of AI and silicon engineering.


• Position based in Barcelona, open to other European locations like Rome (Italy)

We're looking for exceptional engineers ready to shape the future of AI infrastructure. If building scalable, cloud-native AI deployment platforms excites you, we'd love to meet you. At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential---regardless of race, gender, ethnicity, sexual orientation, or gender identity.