Senior GLS & Hardware Emulation Verification Engineer

Semidynamics; Barcelona; Presencial; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Barcelona office

WFH one day per week

Work from anywhere week

Competitive package

Descripción de la vacante

Seynamics in Barcelona, Spain seeks a Design Verification Engineer to support gate-level simulations and hardware emulation for AI chip verification teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoCs prior to tapeout.

This hands-on role requires close collaboration with RTL, DFT, physical design, and firmware teams. Senior position with emphasis on GLS and emulation, testbench development, and regression management.

Formación

• Bachelors or Masters in Electrical/Computer Engineering or related field.
• 3+ years in ASIC/SoC design verification with gate-level exposure.
• Hands-on with hardware emulation platforms (Palladium/ZeBu/Veloce) or FPGA prototyping.
• Strong understanding of digital design: clocking, resets, low-power (UPF/CPF), STA concepts.
• Proficiency with Verilog/SystemVerilog and simulators (VCS, Xcelium, Questa).
• Experience with SDF back-annotation and timing-accurate gate-level simulation.
• Scripting in Perl, Python, or TCL for flows and debug.
• Version control (Git/Perforce) and job scheduling (LSF/Grid).
• Strong debugging skills and ability to work independently on complex problems.

Responsabilidades

• Set up, run, and debug GLS for functional and timing verification across design blocks and full-chip levels.
• Support hardware emulation platforms (Siemens Veloce) including compile, bring-up, debug, and regression management.
• Debug RTL vs GLS mismatches, X-propagation, timing violations, glitches, and clock/reset domain issues.
• Develop and maintain testbenches, scripts, and flows to automate GLS and emulation cycles.
• Collaborate with DFT engineers to validate scan, ATPG patterns, and BIST in GLS and emulation.
• Work with physical design and STA teams to resolve SDF annotation and timing issues.
• Bring up emulation models for pre-silicon software/firmware validation and profiling.
• Triage and root-cause simulation/emulation failures; track bugs and drive fixes.
• Optimize runtimes, capacity, and compile turnaround for large SoC designs.
• Maintain documentation of GLS/emulation methodologies and issues.

Conocimientos

Gate-level verification

Verilog/SystemVerilog

Debugging skills

Scripting (Perl, Python, TCL)

RTL/GPU timing awareness

SoC verification experience

Educación

Bachelor's or Master's in Electrical/Computer Engineering

Herramientas

Veloce

Palladium

ZeBu

FPGA-based prototyping

VCS/Questa/Xcelium

Descripción del empleo

Seynamics in Barcelona, Spain seeks a Design Verification Engineer to support gate-level simulations and hardware emulation for AI chip verification teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoCs prior to tapeout.

This hands-on role requires close collaboration with RTL, DFT, physical design, and firmware teams. Senior position with emphasis on GLS and emulation, testbench development, and regression management.