Senior Design Verification Engineer: PCIe/UCIe AMBA, Hybrid

Hireroo; Barcelona; Hybrid; EUR 110,000 - 150,000; Full time

Benefits offered by this job

Flexible working hours

Hybrid model

Relocation bonus

Private medical insurance

Visa support

Housing search support

Virtual shares

Language classes

Tax incentive

Job summary

Hireroo Ltd. in Barcelona, Spain, is seeking a Staff Design Verification Engineer to develop and enhance functional verification environments for ASIC/SoC designs, focusing on PCIe, UCIe, SerDes and AMBA protocols.

The role requires ownership of SystemVerilog/UVM testbenches, protocol verification, debugging and coverage closure. The position is senior and collaborative, with RTL and architecture teams, offering a hybrid work model (4 days in office, 1 day from home) and a competitive package.

Qualifications

• 7+ years in ASIC/SoC functional verification.
• Recent PCIe, UCIe or SerDes verification experience.
• Strong AMBA knowledge (AXI/CHI/CXS/AHB).
• Advanced SystemVerilog, UVM and coverage closure skills.
• Experience with simulation tools (VCS/Xcelium/Questa).
• Independent technical ownership and complex problem solving.

Responsibilities

• Develop and debug ASIC/SoC verification environments at IP and subsystem levels.
• Build and maintain SystemVerilog/UVM testbenches.
• Verify PCIe, UCIe, SerDes and AMBA protocols.
• Investigate RTL, verification model and specification mismatches.
• Drive functional coverage, regressions and bug closure.
• Improve simulation performance and automate verification workflows.
• Resolve complex verification issues with engineering teams.
• Maintain verification documentation and methodologies.

Skills

SystemVerilog/UVM

RTL debugging

Protocol verification

Independent ownership

Problem solving

Education

Engineering degree

Tools

VCS

Xcelium

Questa

Job description

Hireroo Ltd. in Barcelona, Spain, is seeking a Staff Design Verification Engineer to develop and enhance functional verification environments for ASIC/SoC designs, focusing on PCIe, UCIe, SerDes and AMBA protocols.

The role requires ownership of SystemVerilog/UVM testbenches, protocol verification, debugging and coverage closure. The position is senior and collaborative, with RTL and architecture teams, offering a hybrid work model (4 days in office, 1 day from home) and a competitive package.