Lead DDR/LPDDR Verification Architect (UVM)

Hireroo; Barcelona; Hybrid; EUR 100,000 - 150,000; Full time

Benefits offered by this job

Flexible hours

Hybrid work

Relocation bonus

Private medical insurance

Housing search support

Visa support

Language classes

Tax incentive

Job summary

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs.

Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure functional correctness and protocol compliance.

Qualifications

• 10+ years in ASIC/SoC functional verification.
• DDR/LPDDR or comparable high speed protocol verification.
• AMBA protocol knowledge including AXI, AHB, CHI or CXS.
• SystemVerilog, UVM and coverage closure experience.
• Experience with VCS, Xcelium or Questa.
• RTL debugging and SoC architecture knowledge.
• Technical leadership and team coordination.
• Relevant engineering degree.

Responsibilities

• Lead functional verification of DDR/LPDDR memory interfaces at IP and subsystem levels.
• Develop and maintain SystemVerilog/UVM testbenches.
• Define verification strategies, coverage plans and signoff criteria.
• Verify DDR/LPDDR and AMBA protocol compliance.
• Debug RTL, testbench and specification mismatches.
• Manage regressions, investigate failures and drive bug closure.
• Optimize simulation performance and automate verification workflows.
• Guide verification engineers and collaborate across engineering teams.
• Maintain verification documentation and methodologies.

Skills

ASIC/SoC verification

DDR/LPDDR verification

AMBA protocol knowledge

SystemVerilog/UVM

RTL debugging

Leadership

Team coordination

Education

Engineering degree

Tools

VCS

Xcelium

Questa

Job description

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs.

Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure functional correctness and protocol compliance.