Senior ASIC Lead - SoC Architecture & Security

Cipherbit - Grupo Oesía; Rivas-Vaciamadrid; Vor Ort; EUR 90.000 - 120.000; Vollzeit

Zusammenfassung

Cipherbit-Grupo Oesía is seeking a technical lead for ASIC/SoC development in Madrid to design, integrate IPs and drive end-to-end project execution.

You will coordinate multidisciplinary teams, oversee Front-End and Back-End flows, and collaborate with foundries, design houses and technology providers to meet complex requirements.

We value strong leadership, experience with Cadence/Synopsys/Siemens EDA tools, UVM verification, DFT/ATPG, and successful tape-outs.

Qualifikationen

• Solid experience in ASIC development and complete development cycles.
• Experience in the design and integration of complex SoCs, RISC-V, ARM or equivalent architectures.
• Knowledge of Front-End and/or Back-End flows and UVM verification methodologies.
• Experience in DFT, ATPG, MBIST/LBIST and silicon validation.
• Experience with Cadence, Synopsys or Siemens EDA tools.
• Ability to provide technical leadership and coordinate multidisciplinary teams.

Aufgaben

• Technically lead the development of highly complex ASICs.
• Define ASIC/SoC architectures and integrate IPs and subsystems.
• Coordinate the design, verification, physical implementation, tape-out and validation phases.
• Oversee Front-End and Back-End development flows.
• Coordinate multidisciplinary teams and collaborate with foundries, design houses and technology providers.
• Act as the technical lead, ensuring compliance with project requirements.

Kenntnisse

ASIC development

SoC design

Leadership

UVM verification

Tools

Cadence tools

Synopsys tools

Siemens EDA

Jobbeschreibung

Cipherbit-Grupo Oesía is seeking a technical lead for ASIC/SoC development in Madrid to design, integrate IPs and drive end-to-end project execution.

You will coordinate multidisciplinary teams, oversee Front-End and Back-End flows, and collaborate with foundries, design houses and technology providers to meet complex requirements.

We value strong leadership, experience with Cadence/Synopsys/Siemens EDA tools, UVM verification, DFT/ATPG, and successful tape-outs.