Senior RTL ASIC & SoC Design Engineer

Oesía Group; Rivas-Vaciamadrid; On-site; EUR 55,000 - 85,000; Full time

Job summary

Grupo Oesía is looking for a skilled engineer to join a multidisciplinary team to design, develop and integrate high-value ASIC/SoC solutions that make a real impact for clients in strategic sectors.

You will contribute to RTL design, participate in complete ASIC lifecycles, work with RISC-V/ARM architectures and verify with advanced UVM methodologies, while collaborating with frontend/backend and test teams.

Qualifications

• Degree in Telecommunications Engineering, Electronics, Industrial Engineering, Computer Engineering or related field.
• Experience in digital design within ASIC/SoC environments.
• Participation in one or more complete ASIC development lifecycles.
• Experience with ASIC tape-outs and IC fabrication.
• Experience with SoCs based on RISC-V/ARM.
• Experience with third-party IP integration.
• Knowledge of Front-End/Back-End ASIC flows.
• Experience in verification environments using UVM.
• Knowledge of DFT/ATPG/MBIST and silicon validation.
• Experience with Cadence, Synopsys or Siemens EDA environments.
• Experience collaborating with multidisciplinary teams across design, verification, physical implementation and test.

Responsibilities

• Design, develop and integrate technological solutions for high-value client projects.
• Contribute to RTL design of complex ASIC and SoC solutions.
• Collaborate on Front-End ASIC development flows and with Back-End and physical implementation teams.
• Work with verification engineers using advanced UVM methodologies.
• Contribute to activities related to DFT, ATPG, MBIST/LBIST and silicon validation.
• Participate in ASIC development leading toward tape-out and fabrication.
• Collaborate with architecture, RTL design, verification, physical implementation and test teams.

Skills

RTL design

ASIC/SoC experience

UVM methodologies

DFT/ATPG/MBIST

Team collaboration

Education

Electronics/Telecommunications/Industrial/Computer Engineering degree

Tools

Cadence tools

Synopsys tools

Siemens EDA tools

RISC-V/ARM architectures

Job description

Grupo Oesía is looking for a skilled engineer to join a multidisciplinary team to design, develop and integrate high-value ASIC/SoC solutions that make a real impact for clients in strategic sectors.

You will contribute to RTL design, participate in complete ASIC lifecycles, work with RISC-V/ARM architectures and verify with advanced UVM methodologies, while collaborating with frontend/backend and test teams.