Hybrid FPGA Engineer - Mid Level, Flexible Hours & Perks

Hireroo Ltd; Barcelona; Híbrido; EUR 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible working hours

Hybrid model: 4 days in office, 1 day

Relocation bonus

Housing search support

Visa support if required

Family relocation support

Private medical insurance

Virtual shares

Language classes

Tax incentive

Descripción de la vacante

Hireroo Ltd in Barcelona, Spain, is seeking an FPGA Engineer to support FPGA prototyping and emulation of advanced processor designs. The role focuses on integrating RTL into FPGA platforms, configuring peripherals, developing RTL modules and supporting debugging, validation and demonstration systems.

You should have 3+ years of FPGA experience with Xilinx or Altera devices, Verilog or SystemVerilog, and hands-on skills with Vivado or Quartus, TCL, Bash, Git and Linux.

Formación

• 3+ years of FPGA experience with RTL in FPGA platforms.
• Experience with Xilinx or Altera devices and RTL languages (Verilog/SystemVerilog).
• Proficiency in Vivado/Quartus, TCL and Bash scripting.
• Version control with Git and Linux environment familiarity.

Responsabilidades

• Integrate RTL releases into FPGA designs.
• Configure FPGA peripherals for performance.
• Develop RTL modules for emulation and prototyping.
• Support RISC V processor prototyping.
• Translate requirements into FPGA solutions.
• Maintain and improve FPGA platforms and resources.
• Support demonstration and validation systems.
• Debug FPGA hardware and interfaces.

Conocimientos

3+ years FPGA experience

Xilinx or Altera FPGAs

Verilog or SystemVerilog

Tcl and Bash

Git

Linux

AXI4, AXI4 Lite, UART, I2C, SPI

Integrated Logic Analyzer (ILA)

Hardware debugging

Educación

Bachelor or Master in Computer Engineering, Electronics, Telecommunications or related field

Herramientas

Vivado

Quartus

Descripción del empleo

Hireroo Ltd in Barcelona, Spain, is seeking an FPGA Engineer to support FPGA prototyping and emulation of advanced processor designs. The role focuses on integrating RTL into FPGA platforms, configuring peripherals, developing RTL modules and supporting debugging, validation and demonstration systems.

You should have 3+ years of FPGA experience with Xilinx or Altera devices, Verilog or SystemVerilog, and hands-on skills with Vivado or Quartus, TCL, Bash, Git and Linux.