Design Verification Engineer – GLS & Hardware Emulation at Semidynamics

Semidynamics; Barcelona; Presencial; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Barcelona office

WFH one day per week

Work from anywhere week

Competitive package

Descripción de la vacante

Seynamics in Barcelona, Spain seeks a Design Verification Engineer to support gate-level simulations and hardware emulation for AI chip verification teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoCs prior to tapeout.

This hands-on role requires close collaboration with RTL, DFT, physical design, and firmware teams. Senior position with emphasis on GLS and emulation, testbench development, and regression management.

Formación

• Bachelors or Masters in Electrical/Computer Engineering or related field.
• 3+ years in ASIC/SoC design verification with gate-level exposure.
• Hands-on with hardware emulation platforms (Palladium/ZeBu/Veloce) or FPGA prototyping.
• Strong understanding of digital design: clocking, resets, low-power (UPF/CPF), STA concepts.
• Proficiency with Verilog/SystemVerilog and simulators (VCS, Xcelium, Questa).
• Experience with SDF back-annotation and timing-accurate gate-level simulation.
• Scripting in Perl, Python, or TCL for flows and debug.
• Version control (Git/Perforce) and job scheduling (LSF/Grid).
• Strong debugging skills and ability to work independently on complex problems.

Responsabilidades

• Set up, run, and debug GLS for functional and timing verification across design blocks and full-chip levels.
• Support hardware emulation platforms (Siemens Veloce) including compile, bring-up, debug, and regression management.
• Debug RTL vs GLS mismatches, X-propagation, timing violations, glitches, and clock/reset domain issues.
• Develop and maintain testbenches, scripts, and flows to automate GLS and emulation cycles.
• Collaborate with DFT engineers to validate scan, ATPG patterns, and BIST in GLS and emulation.
• Work with physical design and STA teams to resolve SDF annotation and timing issues.
• Bring up emulation models for pre-silicon software/firmware validation and profiling.
• Triage and root-cause simulation/emulation failures; track bugs and drive fixes.
• Optimize runtimes, capacity, and compile turnaround for large SoC designs.
• Maintain documentation of GLS/emulation methodologies and issues.

Conocimientos

Gate-level verification

Verilog/SystemVerilog

Debugging skills

Scripting (Perl, Python, TCL)

RTL/GPU timing awareness

SoC verification experience

Educación

Bachelor's or Master's in Electrical/Computer Engineering

Herramientas

Veloce

Palladium

ZeBu

FPGA-based prototyping

VCS/Questa/Xcelium

Descripción del empleo

This Full time on site position offers great opportunities for career growth.

ID: GLS-1

About the Role

We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. In this role, you will help ensure silicon correctness by validating post-synthesis netlists, debugging timing and reset issues, and enabling large-scale emulation of SoC designs prior to tapeout. This is a hands‑on role requiring close collaboration with RTL design, DFT, physical design, and firmware teams.

Key Responsibilities

• Set up, run, and debug gate-level simulations (GLS) for functional, timing (SDF back-annotated), and low-power verification across multiple design blocks and full-chip levels.
• Support hardware emulation platforms Siemens Veloce including design compilation, bring-up, debug, and regression management.
• Debug mismatches between RTL and gate-level simulation results, including X-propagation, timing violations, glitches, and clock/reset domain issues.
• Develop and maintain testbenches, scripts, and flows to automate GLS and emulation compile/run cycles.
• Collaborate with DFT engineers to validate scan, ATPG patterns, and BIST in gate-level and emulation environments.
• Work with physical design and STA teams to resolve SDF annotation, timing exceptions, and back-annotated simulation discrepancies.
• Bring up emulation models for pre-silicon software/firmware validation and performance profiling.
• Triage and root-cause simulation/emulation failures, track bugs, and drive issues to closure with cross-functional teams.
• Optimize simulation and emulation runtimes, capacity, and compile turnaround for large SoC designs
• Maintain documentation of GLS/emulation methodologies, flows, and known issues.

Why Seynamics?

Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Se* ynamics.

• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.

Requirements

Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in ASIC/SoC design verification, with direct exposure to gate-level simulation. Hands‑on experience with at least one hardware emulation platform (Palladium, ZeBu, Veloce) or FPGA‑based prototyping. Strong understanding of digital design fundamentals: clocking, reset strategies, low‑power design (UPF/CPF), and STA concepts Proficiency with Verilog/SystemVerilog and simulation tools (e.g., VCS, Xcelium, Questa). Experience with SDF back-annotation and timing-accurate gate-level simulation Scripting skills in Perl, Python, or TCL for flow automation and debug. Familiarity with version control (Git/Perforce) and job scheduling systems (LSF/Grid). Strong debugging skills and ability to work independently on complex, ambiguous problems.

Preferred Qualifications

• Experience with DFT flows (scan insertion, ATPG, MBIST) and their validation in GLS/emulation.
• Exposure to UVM-based verification methodologies.
• Experience bringing up firmware or software on emulation platforms.
• Familiarity with low-power verification (UPF-based simulation, power-aware GLS).
• Experience working on large multi-million gate SoC designs.
• Knowledge of physical design flows and their interaction with timing closure

SENIOR