Design Verification Engineer, GLS & Hardware Emulation

Hireroo Ltd; Barcelona; Hybrid; EUR 65,000 - 95,000; Full time

Benefits offered by this job

Flexible working hours

Hybrid model

1 week per year working from anywhere

25 days annual leave plus December 24/

December 31

Monthly food allowance

Private medical insurance

Relocation bonus

Housing search support

Visa support

Family relocation support

Virtual shares

Language classes

Tax incentive

Job summary

Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon.

Mid to senior level, you will optimize simulation performance, automate workflows, debug RTL/netlist mismatches, and support emulation bring-up on hardware platforms while contributing to power, timing and

Qualifications

• 3+ years of ASIC or SoC verification experience
• Degree in Electrical or Computer Engineering or related field
• Practical gate level simulation experience
• Hardware emulation or FPGA prototyping experience
• Verilog/SystemVerilog
• VCS, Xcelium or Questa
• SDF annotation and timing simulation
• Clocking, reset and STA fundamentals
• Low power concepts, UPF/CPF
• Python, Perl or TCL scripting
• Git/Perforce and LSF/Grid
• Strong debugging and problem solving skills

Responsibilities

• Configure and debug gate level simulations (GLS)
• Perform functional, timing and power verification
• Support hardware emulation and system bring-up
• Debug RTL and netlist mismatches
• Investigate timing, reset and X propagation issues
• Implement SDF timing annotation
• Automate simulation and emulation workflows
• Support scan, ATPG and BIST verification
• Enable firmware testing through emulation
• Improve simulation performance and regression efficiency
• Collaborate with RTL, DFT and physical design teams

Skills

ASIC/SoC verification

Verilog/SystemVerilog

Scripting (Python/TCL/Perl)

Debugging and problem solving

Gate level simulation

Timing closure knowledge

Education

Degree in Electrical or Computer Engineering

Tools

VCS

Xcelium

Questa

Job description

Job Description

Our partner is looking for a Design Verification Engineer to support gate level simulation and hardware emulation for advanced semiconductor designs.

The role focuses on validating synthesized designs, identifying timing and functional issues, and supporting hardware emulation before silicon production. You will collaborate with RTL, DFT, physical design and firmware teams.

Location: Barcelona, Spain, Hybrid

Level: Mid / Senior, depending on experience

Responsibilities

• Configure and debug gate level simulations (GLS)

• Perform functional, timing and power verification

• Support hardware emulation and system bring-up

• Debug RTL and netlist mismatches

• Investigate timing, reset and X propagation issues

• Implement SDF timing annotation

• Automate simulation and emulation workflows

• Support scan, ATPG and BIST verification

• Enable firmware testing through emulation

• Improve simulation performance and regression efficiency

• Collaborate with RTL, DFT and physical design teams

Requirements

• 3+ years of ASIC or SoC verification experience

• Degree in Electrical or Computer Engineering or related field

• Practical gate level simulation experience

• Hardware emulation or FPGA prototyping experience

• Verilog/SystemVerilog

• VCS, Xcelium or Questa

• SDF annotation and timing simulation

• Clocking, reset and STA fundamentals

• Low power concepts, UPF/CPF

• Python, Perl or TCL scripting

• Git/Perforce and LSF/Grid

• Strong debugging and problem solving skills

Optional / Desired

• Siemens Veloce, Cadence Palladium or Synopsys ZeBu

• UVM verification

• DFT, scan, ATPG and MBIST

• UPF simulation and power verification

• Firmware bring-up on emulation

• Large SoC verification

• Physical design and timing closure knowledge

• Emulation performance optimization

What's in it for you?

• Flexible working hours

• Hybrid model, 4 days office, 1 day from home

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• Monthly food allowance

• Private medical insurance

• Relocation bonus

• Housing search support

• Visa support, subject to approval

• Family relocation support, subject to eligibility

• Virtual shares, subject to plan terms

• Language classes

• Tax incentive, subject to eligibility