ASIC Design Engineer — RTL/Verilog, Hybrid Work & Relocation

GMV; Tres Cantos; Híbrido; EUR 35.000 - 50.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible start and finish times

National and international mobility

Wellbeing program

Descripción de la vacante

GMV based in Tres Cantos is seeking graduates in Electronic Engineering, Telecommunications or Computer Science for roles focused on receiver technology. The position emphasizes digital hardware programming and entails defining ASIC architectures, developing RTL blocks, and optimizing internal interfaces.

The company offers a hybrid working model, competitive compensation, wellness programs, and supports career development and language learning.

If interested, contact Carolina Barber Caso for more information.

Formación

• Graduates in Electronic Engineering, Telecommunications, Computer Science, or similar.
• Knowledge of digital hardware programming is required.
• Experience with ASIC flow and simulation tools is desired.

Responsabilidades

• Define and evolve the target architecture for ASIC.
• Develop and adapt RTL blocks.
• Analyze and optimize internal interfaces.

Conocimientos

Digital RTL design

FPGA architectures

ASIC flow experience

Simulation and synthesis tools

Embedded ARM/RISC-V processors

Educación

Graduate in Electronic Engineering

Graduate in Telecommunications

Graduate in Computer Science

Herramientas

Synopsys

Cadence

Vivado

Vitis

Descripción del empleo

GMV based in Tres Cantos is seeking graduates in Electronic Engineering, Telecommunications or Computer Science for roles focused on receiver technology. The position emphasizes digital hardware programming and entails defining ASIC architectures, developing RTL blocks, and optimizing internal interfaces.

The company offers a hybrid working model, competitive compensation, wellness programs, and supports career development and language learning.

If interested, contact Carolina Barber Caso for more information.