Senior RTL Engineer - VLSI Design, Flexible Hours & Growth

Capgemini Engineering; Madrid; Presencial; EUR 70.000 - 95.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical services

Eye glasses coverage

Meal tickets

Employee Assistance Program

Employee Share Option Plan

Descripción de la vacante

Capgemini Engineering Madrid is seeking a Senior RTL Engineer to lead feasibility studies, define system architecture and interfaces, and drive design from architecture to tape-out. You will perform RTL coding in Verilog/SystemVerilog (or VHDL), develop microarchitecture, and collaborate with Synthesis, STA, PD, and DFT teams to meet timing, power and area goals.

You'll benefit from a collaborative culture, flexible growth opportunities, and a comprehensive benefits package in a global

Formación

• 8+ years in VLSI design.
• BSc/ MSc in Electrical or Computer Engineering.
• Strong Verilog/SystemVerilog or VHDL skills.
• Experience defining microarchitecture and complex units.
• SoC design experience.
• Proficiency with backend tools (Synthesis, STA).
• Familiar with ARM/RISC-V/x86 instruction sets.
• Proficiency in Perl/Python scripting.
• Good communication skills.

Responsabilidades

• Own feasibility studies to define architecture, requirements, interfaces.
• Develop microarchitecture and logic design from architecture to tape-out.
• RTL coding, lint checks, CDC tests, timing constraint files.
• Work with Synthesis, STA, PD, and DFT teams to meet specs.
• Develop flows and tools to support design activities.

Conocimientos

VLSI design

Verilog/SystemVerilog

VHDL

Microarchitecture design

SoC design

Backend design tools (Synthesis/STA)

CPU instruction set familiarity (ARM/R

Scripting (Perl/Python)

Communication skills

Educación

BSc in Electrical/Computer Engineering

MSc in Electrical/Computer Engineering

Herramientas

Synthesis tools

Static Timing Analysis (STA) tools

Descripción del empleo

Capgemini Engineering Madrid is seeking a Senior RTL Engineer to lead feasibility studies, define system architecture and interfaces, and drive design from architecture to tape-out. You will perform RTL coding in Verilog/SystemVerilog (or VHDL), develop microarchitecture, and collaborate with Synthesis, STA, PD, and DFT teams to meet timing, power and area goals.

You'll benefit from a collaborative culture, flexible growth opportunities, and a comprehensive benefits package in a global