Embedded RTL Engineer – ASIC/FPGA Innovation

GMV Spain; Madrid; Hybrid; EUR 50,000 - 75,000; Full time

Benefits offered by this job

Hybrid working model

Relocation package

Wellbeing program

Job summary

GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. The role emphasizes RTL development, IP integration, and extensive ASIC flow activities in a cutting-edge hardware environment.

We value candidates with hands-on experience in digital hardware programming, SystemVerilog-based verification, and familiarity with industry tools (Synopsys, Cadence, Vivado). Hybrid working model and relocation support offered.

Qualifications

• Bachelors degree in Electronic Engineering, Telecom or CS with focus on digital hardware programming.
• Experience with digital RTL design, FPGA/SoC/MPSoC architectures and IP integration.
• Familiarity with ASIC flow, simulation and synthesis tools, and SystemVerilog/UVM.
• Knowledge of STA, DFT, scan, low-power techniques and backend tools is a plus.

Responsibilities

• Define and evolve the target ASIC architecture for the project.
• Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog).
• Analyze internal interfaces, buses, memories, clocks and resets.
• Participate in functional verification, simulation, and design debugging.
• Support the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT and design closure.

Skills

digital RTL design

FPGA

SoC/MPSoC architectures

IP integration

functional verification

ASIC flow

simulation & synthesis tools

SystemVerilog

Education

Electronic Engineering or Telecommunications or Computer Science degree

Tools

Synopsys

Cadence

Siemens EDA

Vivado

Vitis

Job description

GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution. The role emphasizes RTL development, IP integration, and extensive ASIC flow activities in a cutting-edge hardware environment.

We value candidates with hands-on experience in digital hardware programming, SystemVerilog-based verification, and familiarity with industry tools (Synopsys, Cadence, Vivado). Hybrid working model and relocation support offered.