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Capgemini Engineering Madrid is seeking a Senior RTL Engineer to lead feasibility studies, define system architecture and interfaces, and drive design from architecture to tape-out. You will perform RTL coding in Verilog/SystemVerilog (or VHDL), develop microarchitecture, and collaborate with Synthesis, STA, PD, and DFT teams to meet timing, power and area goals.
You'll benefit from a collaborative culture, flexible growth opportunities, and a comprehensive benefits package in a global
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
Are you in search of a new challenge? Are you equipped with a forward-thinking spirit and experienced in digital design flows and tools? Register Transfer Level (RTL) has a multi‑lateral spectrum of increasing complexity which involves a deep understanding of cutting‑edge designs and technologies, methods, and developing flows and tools as necessary in support of the design process.
Capgemini is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.