Memory Layout Engineer (Germany)

leadIC Design Pvt Ltd; Deutschland; Vor Ort; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

leadIC Design Pvt Ltd in Germany seeks a Memory Layout Engineer with 5-7 years of hands-on experience in memory layout design on lower technology nodes. You will develop, verify, and optimize SRAM memory blocks, ensuring adherence to DRC/LVS and density requirements while collaborating with circuits teams for efficient tape-outs.

The role emphasizes cross-functional teamwork and refining layouts for optimal performance, power, and area (PPA) across multiple process nodes.

Qualifikationen

• 5-7 years of memory layout engineering experience.
• Strong experience in lower technology nodes.
• Hands-on with DRC/LVS closure.
• Good understanding of semiconductor layout fundamentals.

Aufgaben

• Perform memory layout design for SRAM and memory blocks.
• Work on lower technology nodes.
• Ensure layouts meet DRC, LVS and density requirements.
• Optimize layout for performance, power, and area (PPA).
• Collaborate with circuit design and verification teams.
• Support tape-out activities and resolve layout issues.

Kenntnisse

Memory layout engineering

Lower nodes experience

DRC/LVS closure

Semiconductor layout fundamentals

Jobbeschreibung

Experience: 5-7 Years
Location: Germany
Domain: Semiconductor / Memory Design

Role Overview

We are looking for a Memory Layout Engineer with 5-7 years of hands-on experience in memory layout design, specifically on lower technology nodes. The role involves layout development, verification, and close collaboration with design and verification teams.

Key Responsibilities

• Perform memory layout design for SRAM / memory blocks

• Work on lower technology nodes (mandatory)

• Ensure layout meets DRC, LVS, and density requirements

• Optimize layout for performance, power, and area (PPA)

• Collaborate with circuit design and verification teams

• Support tape-out activities and resolve layout-related issues

Mandatory Skills

• 5-7 years of experience in memory layout engineering

• Strong experience in lower nodes (mandatory)

• Hands-on with DRC/LVS closure

• Good understanding of semiconductor layout fundamentals

Good to Have

• Experience with advanced memory architectures

• Exposure to multiple process nodes

• Strong communication and teamwork skills