Analog IC Layout Engineer

Intellectual Capital Resources Ltd; Bayern; Vor Ort; EUR 70.000 - 100.000; Vollzeit

Zusammenfassung

Intellectual Capital Resources Ltd in Bavaria seeks an experienced Analog IC Layout Engineer to contribute to brain-computer interfaces and implantable chips for HealthTech.

Open to junior through senior candidates with a work permit for Germany and EU residency. The role offers opportunities to work on cutting-edge health-tech hardware in a collaborative, innovation-driven environment.

Qualifikationen

• A degree in Electrical Engineering, Microelectronics, Physics, or a related field.
• Silicon-proven analog and mixed-signal layout designs, achieving tight matching and low noise.
• Solid understanding of semiconductor device physics and CMOS microfabrication process.
• Expertise in full physical verification flows (DRC, LVS, ERC, PEX) using industry standard EDA tools.
• Expertise in precision analog layout techniques (matching, isolation, shielding).
• Deep understanding of layout-dependent effects, especially in highly compact, multi-channel neural SoCs.

Kenntnisse

Analog/mixed-signal layout

Matching & low-noise design

CMOS device physics

Physical verification (DRC/LVS/ERC/PEX

Layout-dependent effects

Ausbildung

Electrical Engineering

Microelectronics

Physics

Tools

EDA tools

Jobbeschreibung

We are seeking a highly skilled and motivated Analog IC Layout Engineer to join our team in developing the next generation of brain-computer interfaces. This role offers the opportunity to contribute to groundbreaking advancements in HealthTech, working on implantable chips that will transform lives and push the limits of innovation. Junior to senior level experience will be considered and only candidates with a work permit for Germany and based in the EU will be considered.

To be considered for this role you have the following experience:

• A degree in Electrical Engineering, Microelectronics, Physics, or a related field
• Silicon-proven analog and mixed-signal layout designs (particularly for amplifiers and data converters), achieving tight matching and low noise
• Solid understanding of semiconductor device physics and CMOS microfabrication process
• Expertise in full physical verification flows (DRC, LVS, ERC, PEX) using industry standard EDA tools
• Expertise in precision analog layout techniques (matching, isolation, shielding)
• Deep understanding of layout-dependent effects, especially in highly compact, multi-channel neural SoCs