ASIC Analog Layout Engineer (m/f/d) - REF5390S

AUMOVIO SE Haupverwaltung; Frankfurt; On-site; EUR 55,000 - 75,000; Full time

Job summary

A leading tech company in Frankfurt is seeking an experienced ASIC Layout Engineer to drive the top-level integration of analog and mixed-signal ICs. The role requires strong expertise in layout design, particularly in BCD technologies, and collaboration with design engineers for optimal chip performance. Candidates must possess an academic degree in Electronics Engineering and extensive experience in analog layout design. Fluent English is essential, and German skills are advantageous.

Qualifications

• Academic degree in Electronics Engineering or related field is required.
• Extensive professional experience in analog layout design.
• Proven experience in top-level layout integration.

Responsibilities

• Drive the top-level layout integration of analog/mixed-signal chips.
• Define top-level floorplan and padframe design.
• Collaborate with design engineers to meet specifications.

Skills

Analog layout design

Top-level layout integration

BCD technologies

Deep submicron effects understanding

Layout tools proficiency

English language skills

German language skills

Education

Academic degree in Electronics Engineering

Tools

Layout design software

Job description

Company Description

At AUMOVIO, we own what we do: Developing and producing hardware, software, and services that shape the future of mobility. But what truly sets us apart are our people. People who thrive in our winning culture, driven by bold ideas. People who take a leap and create meaningful difference—together. Because we believe that the future belongs to those who own it. That’s why we foster a culture where you own every step of the way.

Own your career, your growth, your skills, and your impact. Join us and own what’s next.

Advanced Electronics & Semiconductor Solutions (AESS) organization has been established in AUMOVIO to develop and manufacture semiconductors in a fabless model to fulfilling strategic internal semiconductor demands.

Job Description

As an ASIC Layout Engineer (m/f/diverse) for AESS (Advanced Electronics & Semiconductor Solutions), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.

Key Responsibilities

• Drive the top-level layout integration of analog/mixed-signal chips (analog on top)
• Define toplevel floorplan, padframe design and bonding diagrams in coordination with other domains
• Coordinate with other layouters to define floorplans according to the chip top level
• Generate and integrate analog layouts at block and chip level
• Perform pin placement, parasitic extraction, and layout optimization
• Ensure compliance with DRC, LVS, and support tape-out activities
• Collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements

Qualifications

• Academic degree in Electronics Engineering or related field
• Extensive professional experience in analog layout design
• Proven experience in top-level layout integration
• Strong expertise in BCD technologies (65nm to 180nm)
• Deep understanding of deep submicron effects (parasitics, coupling, matching)
• Proficient in layout tools for design, DRC, LVS, and extraction
• Knowledge of analog circuit design
• Fluent English language skills (both written and spoken), German language skills are a plus

Applications from severely handicapped people are welcome.