Layout Engineer

European Tech Recruit

Aachen

Vor Ort

EUR 60.000 - 80.000

Vollzeit

14 Tage+
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Zusammenfassung

A technology recruitment firm seeks a talented Layout Engineer in Aachen to manage the physical layout of high-performance analog circuits. Candidates should hold an M.Sc. or Ph.D. in Electrical Engineering and possess experience in mixed-signal layouts. Proficiency in Cadence design tools and strong communication skills are essential. This full-time position offers opportunities within an exciting semiconductor startup.

Qualifikationen

  • Experience with high-speed or high-resolution ADC, DAC and PLL layouts.
  • Experience in full-custom IC layout for analogue or mixed-signal circuits.
  • Experience with advanced CMOS process nodes.

Aufgaben

  • Responsible for the physical implementation of Mixed Signal circuits.
  • Optimize layout for matching, low noise, minimal parasitics, and efficient area usage.
  • Collaborate with design teams to ensure physical design meets performance targets.

Kenntnisse

Layout techniques for matching
Understanding of shielding
Proficiency with Cadence design tools
Communication skills

Ausbildung

M.Sc. or Ph.D. in Electrical Engineering or related field

Tools

Cadence design tools

Jobbeschreibung

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Principal Consultant | Software Engineering, AI & CV/ML, Semiconductors & Electronics

Layout Engineer

European Tech Recruit are working closely with an exciting semicon startup, based in Aachen, who are looking for a talented Layout Engineer to join their team.

In this role you will be responsible for the physical layout of high-performance analog and mixed-signal circuits, including blocks such as ADCs, DACs, PLLs, and other analogue/mixed-signal blocks. You will work closely with circuit designers to ensure accurate and optimized implementation, meeting all performance, matching, area, and reliability requirements.

Responsibilities as Layout Engineer:

  • Responsible for the physical implementation of Mixed Signal circuits.
  • Work closely with design engineers in the custom layout, physical design, and verification of high-speed SerDes, PLL, CDR, LVDS, and other mixed-signal integrated circuits.
  • Optimize layout for matching, low noise, minimal parasitics, and efficient area usage.
  • Interpret schematics, floorplans, and layout constraints from design engineers.
  • Perform and resolve DRC, LVS, and ERC violations using industry-standard tools.
  • Generate and validate parasitic extractions (PEX) for post-layout simulation.
  • Collaborate with design teams to ensure physical design meets performance targets.
  • Participate in design and layout reviews; contribute to layout methodology improvements.
  • Ensure layout reliability and manufacturability across PVT corners and process variations.
  • Support IP integration into customer products.

Requirements:

  • M.Sc. or Ph.D. in Electrical Engineering or related field.
  • Experience with high-speed or high-resolution ADC, DAC and PLL layouts.
  • Strong understanding of layout techniques for matching, shielding, routing, and symmetry.
  • Experience in full-custom IC layout for analogue or mixed-signal circuits.
  • Proficiency with Cadence design tools.
  • Experience with advanced CMOS process nodes.
  • Good communication skills and ability to work in a collaborative team environment.

If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)

Seniority level
  • Seniority level
    Mid-Senior level
Employment type
  • Employment type
    Full-time
Job function
  • Job function
    Engineering, Information Technology, and Other
  • Industries
    Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development

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