IC Layout Engineer - High-Performance Mixed-Signal ICs

European Tech Recruit; Aachen; Hybrid; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

A semiconductor-focused recruiting partner is seeking an IC Layout Engineer in Aachen to execute full-custom layouts of high-performance Mixed-Signal circuits including ADCs and DACs. Applicants should have a M.Sc. or Ph.D. in Electrical Engineering, proven experience in layout techniques, and expert skills in the Cadence design suite. The role includes hybrid work flexibility, enabling 2-3 days remote work each week, fostering collaboration in a team environment.

Qualifikationen

• Proven experience with ADC, DAC, and PLL layouts.
• Expertise in high‑speed design and physical implementation.
• Ability to interpret complex schematics.

Aufgaben

• Execute full-custom physical layout of Mixed-Signal circuits.
• Collaborate to optimize layouts.
• Perform DRC, LVS, and ERC violation resolutions.

Kenntnisse

High-speed Mixed-Signal circuits

Layout techniques

Collaboration in teams

DRC/LVS/PEX

Cadence design suite

Ausbildung

M.Sc. or Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

Jobbeschreibung

IC Layout Engineer - High-Performance Mixed-Signal ICs

We are partnered with a specialized semiconductor company focused on the development of high-performance Mixed‑Signal IP. The team are looking to hire an IC Layout Engineer within their design team to work on the physical implementation of critical blocks—including ADCs, DACs, and PLLs—across advanced process nodes such as 22FDX, FinFET, and FD‑SOI.

This is a permanent opportunity based in Aachen (hybrid work of 2‑3 days per week remote is possible).

Key Responsibilities

• Execute the full‑custom physical layout of high‑speed Mixed‑Signal circuits, including SerDes, PLL, CDR, and LVDS.
• Collaborate with circuit designers to optimize layouts for matching, low noise, minimal parasitics, and efficient area usage.
• Perform and resolve DRC, LVS, and ERC violations using industry‑standard tools to ensure tape‑out readiness.
• Generate and validate Parasitic Extractions (PEX) for critical post‑layout simulations.
• Ensure layout manufacturability and reliability across PVT corners and advanced process variations.
• Participate in layout reviews and contribute to the continuous improvement of internal layout methodologies.

Key Requirements

• M.Sc. or Ph.D. in Electrical Engineering or a related technical field.
• Proven experience with high‑speed or high‑resolution ADC, DAC, and PLL layouts.
• Deep understanding of layout techniques for matching, shielding, routing, and symmetry.
• Expert‑level command of the Cadence design suite.
• Significant experience with advanced CMOS process nodes (FinFET, FD‑SOI).
• Ability to interpret complex schematics and collaborate effectively in a cross‑functional team environment.

Keywords: IC Layout Engineer / Analog Layout / Mixed‑Signal / Custom Layout / 22FDX / FinFET / FD‑SOI / ADC / DAC / PLL / SerDes / Cadence Virtuoso / DRC / LVS / PEX / Parasitic Extraction / High‑Speed Design / Physical Implementation / Semiconductor / CMOS

If you are interested in this IC Layout Engineer opportunity, please send a copy of your CV to [e-mail]

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Seniority level

• Mid‑Senior level

Employment type

• Full‑time

Job function

• Engineering and Design

Industries

• Semiconductor Manufacturing
• Computers and Electronics Manufacturing