Senior Analog Layout Design Engineer

microTECH Global Limited; München; Hybrid; EUR 90.000 - 140.000; Vollzeit

Zusammenfassung

microTECH Global Limited in Munich invites an experienced Senior Layout Design Engineer to take ownership of top-level chip planning and custom analogue and digital layout. You will lead integration and physical verification while mentoring junior engineers and coordinating international layout teams.

The role focuses on advanced CMOS/BiCMOS technologies, floorplanning, and ensuring performance, area efficiency and signal integrity across multi-site design activities.

Qualifikationen

• 10+ years' experience in analogue and full-custom IC layout.
• Strong CMOS and BiCMOS layout experience.
• Excellent experience with Cadence Virtuoso.
• Experience with Cadence PVS and/or Mentor Calibre.
• Strong knowledge of DRC, LVS, ERC, parasitics, matching, crosstalk, IR drop and electromigration.
• Experience with chip-level floorplanning and analogue block integration.
• Proven experience taking IC designs through verification and tape-out.

Aufgaben

• Lead top-level chip planning and floorplanning.
• Perform full-custom layout for CMOS and BiCMOS circuits.
• Develop block, sub-block and chip-level layouts.
• Optimise layouts for area, matching, performance and signal integrity.
• Perform power planning, shielding and device matching.
• Manage DRC, LVS and ERC verification.
• Support chip integration, verification and tape-out.
• Review and coordinate work from international/offshore layout teams.
• Mentor junior layout engineers and external contractors.
• Develop and improve layout methodologies and best practices.

Kenntnisse

Analogue & full-custom layout

Cadence Virtuoso

DRC/LVS/ERC verification

Floorplanning

Leadership & mentoring

Scripting/automation

International coordination

Tools

Cadence PVS

Mentor Calibre

Jobbeschreibung

Job title :Senior Layout Design Engineer

Location :Munich, Germany

Job Type :Permanent

Company Overview

Our client is an innovative semiconductor company developing advanced CMOS and BiCMOS technologies for next-generation electronic systems.

The Munich R&D team works alongside international design centres, delivering complex IC solutions from chip planning and layout through verification and tape-out.

The Role

As a Senior Layout Design Engineer, you will take ownership of top-level chip planning, custom analogue and digital layout, chip integration and physical verification.

The role also offers a strong technical leadership element, including mentoring junior engineers and coordinating international layout teams.

Key Responsibilities

• Lead top-level chip planning and floorplanning
• Perform full-custom layout for CMOS and BiCMOS circuits
• Develop block, sub-block and chip-level layouts
• Optimise layouts for area, matching, performance and signal integrity
• Perform power planning, shielding and device matching
• Manage DRC, LVS and ERC verification
• Support chip integration, verification and tape-out
• Review and coordinate work from international/offshore layout teams
• Mentor junior layout engineers and external contractors
• Develop and improve layout methodologies and best practices

Requirements

• 10+ years' experience in analogue and full-custom digital IC layout
• Strong CMOS and BiCMOS layout experience
• Excellent experience with Cadence Virtuoso
• Experience with Cadence PVS and/or Mentor Calibre
• Strong knowledge of DRC, LVS, ERC, parasitics, matching, crosstalk, IR drop and electromigration
• Experience with chip-level floorplanning and analogue block integration
• Proven experience taking IC designs through verification and tape-out

Preferred Experience

• Experience with advanced CMOS/BiCMOS process technologies
• Experience across 180nm, 65nm, 55nm and/or 22nm technologiesExperience mentoring or coordinating other layout engineers
• Scripting/automation experience
• Experience working within international semiconductor design teams

Why Join?

• Take ownership of complex chip-level layout and integration
• Work with advanced CMOS and BiCMOS technologies
• Collaborate with international semiconductor design teams
• Influence layout methodologies and best practices
• Combine hands-on technical work with technical leadership