Digital Design Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; München; Vor Ort; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

TSMC - Taiwan Semiconductor Manufacturing Company Limited in München is seeking a hardware developer for embedded memories. In this role, you will define and implement RTL designs, ensuring feasibility of implementation and supporting the RTL to GDS flow. Candidates should have over 5 years of experience in non-volatile memory design and hold a Master's degree in Electrical Engineering.

Collaboration with P&R teams and the utilization of EDA tools like Synopsys and Cadence are essential. This position offers opportunities for methodology improvements and advances in flow automation.

Qualifikationen

• 5+ years of experience in non-volatile memory circuit or logic design.
• Familiar with EDA tools and design methodology for non-volatile memory.
• Educational background in Electrical Engineering or related majors.

Aufgaben

• Define and document micro-architecture of RTL designs.
• Implement micro-architecture using Verilog/System Verilog.
• Support complete RTL to GDS flow and perform logic synthesis.

Kenntnisse

RTL design

Verilog

System Verilog

EDA tools

Timing optimization

Ausbildung

Master's degree or above in Electrical Engineering

Tools

Synopsys

Cadence

Mentor Graphics

Jobbeschreibung

As part of the hardware development team for embedded memories you develop IPs that will power future products of our customers. In this role you:

Responsibilities

1. Define, explore, and document micro-architecture of RTL designs based on given requirements and specified architecture.
2. Implement the design micro-architecture using synthesizable Verilog or System Verilog according to coding guidelines.
3. Support the complete RTL to GDS flow, ensuring design constraints and feasibility of implementation.
4. Utilize at least one linting tool.
5. Collaborate with the P&R team to specify SDC for synthesis and P&R.
6. Perform logic synthesis, LEC (Logic Equivalency Checking) and STA analysis.
7. Develop, document, and execute verification plan using Verilog, System Verilog and preferably UVM.
8. Utilize industry-standard EDA tools, such as Synopsys, Cadence, or Mentor Graphics.
9. Debug and resolve complex design issues, including timing, power, and area optimization.
10. Collaborate with experienced architects and product engineering team to assess feasibility of ideas and create new ones.
11. Optional but advantageous: Contribute to methodology improvements enhancing flow automation and efficiency by means of scripting or evaluation and utilisation of AI powered tools.

Qualifications

1. Master's degree or above in Electrical Engineering or any related majors.
2. More than 5 years of non-volatile memory (flash memory, RRAM, MRAM, PCRAM) circuit or logic design experience.
3. Familiar with EDA tools and design methodology for custom design or digital design of non-volatile memory.

Only the applications relevant to the criteria above will be taken for further consideration.