ASIC Physical Design, Sr Staff Engineer - 16724

Synopsys Inc; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Synopsys Inc. is seeking an experienced ASIC Physical Design Engineer to drive the implementation of test chips across DDR/HBM/UCIe protocols, from RTL to GDS release.

You will shape floorplans, power/ground strategies, and own the RTL-to-GDSII flow, working with architecture, RTL, circuit, and covercell teams to ensure timing, area, power, and manufacturability targets. You will lead complex, cross-functional projects, coordinate test chip methodologies, and contribute to flow automation and

Qualifications

• 9+ years of experience in ASIC physical design, with a track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the full ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Experience coordinating complex, cross-functional projects and leading technical execution.

Responsibilities

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, RTL to GDS release.
• Developing floorplan and power/ground strategies for diverse test chip architectures.
• Owning RTL-to-GDSII flow and ensuring design convergence for area, power, performance, manufacturability.

Skills

ASIC design

Leadership

Cross-functional teamwork

Tools

Design Compiler

PrimeTime

IC Compiler II/FC

ICV

Calibre

RedHawk

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced ASIC Physical Design Engineer with a passion for innovation and a proven track record in complex SoC and test chip implementations. You thrive in collaborative environments, excel at cross-functional teamwork, and are ready to lead technical execution on advanced process nodes. Your expertise in the physical design flow and familiarity with industry-leading tools make you a valuable contributor to our mission of delivering robust, silicon-proven IP solutions.

What You'll Be Doing:

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
• Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
• Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
• Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
• Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
• Driving tool flow automation and debugging to enhance productivity and design reliability.
• Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.
• Preparing and releasing all supporting views and documentation necessary for tape-out, maintaining mask tooling forms and checklists on foundry portals.

The Impact You Will Have:

• Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
• Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
• Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
• Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
• Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
• Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

What You'll Need:

• 9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Familiarity with IP integration, test chip methodology, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
• Experience coordinating complex, cross-functional projects and leading technical execution.
• Authorization to work in the USA.

Who You Are:

• Analytical thinker with strong problem-solving skills and attention to detail.
• Effective communicator, able to articulate complex technical concepts to diverse stakeholders.
• Collaborative team player, fostering a culture of inclusion and innovation.
• Proactive leader, driving continuous improvement and embracing new technologies.
• Adaptable and resilient, thriving in fast-paced, dynamic environments.
• Committed to excellence and quality in every aspect of design and delivery.

The Team You'll Be A Part Of:

You'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks-logic, memory, interfaces, analog, security, and embedded processors-into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.