Senior ASIC Digital Design Architect — Hybrid/Remote SerDes

Synopsys Inc; Markham; Hybrid; CAD 140,000 - 210,000; Full time

Job summary

Synopsys Inc. in Canada seeks a senior digital ASIC designer to own high-speed SerDes IP blocks and drive RTL design with clock-domain crossing and timing closure. You will partner with verification, DFT, and test teams to ensure robust silicon for Ethernet, PCIe, SATA, and USB PHYs.

You will mentor junior engineers and shape design methodology across groups, with hybrid or remote work options across Canada.

Qualifications

• 10+ years of hands-on digital ASIC design experience.
• Strong RTL coding in Verilog/VHDL with timing constraints.
• Experience with high-speed SerDes and mixed-signal interfaces.
• Collaboration with verification and testplan teams.

Responsibilities

• Architect digital subsystems for high-speed SerDes IP (Ethernet, PCIe, SATA, USB).
• Define interface specs and translate requirements into RTL constraints.
• Lead clock-domain crossing decisions and power optimization strategies.
• Collaborate with ASIC verification to close coverage gaps and debug failures.
• Mentor junior engineers and guide design methodology across teams.

Skills

10+ years experience

Digital ASIC design

Verilog/VHDL

Clock domain crossing

Synthesis & timing

DFT methodologies

Testplan collaboration

ASIC verification

High-speed interfaces

Education

Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Gate-level simulators

Synthesis tools

Job description

Synopsys Inc. in Canada seeks a senior digital ASIC designer to own high-speed SerDes IP blocks and drive RTL design with clock-domain crossing and timing closure. You will partner with verification, DFT, and test teams to ensure robust silicon for Ethernet, PCIe, SATA, and USB PHYs.

You will mentor junior engineers and shape design methodology across groups, with hybrid or remote work options across Canada.