Senior ASIC Physical Design Engineer – PPA & Timing Leader

Ciena Corporation; Ottawa; On-site; CAD 109,000 - 174,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Employee Stock Purchase Program (ESPP)

401(K) / DCPP with company matching

Holidays

Paid sick leave

Vacation time

Job summary

Ciena Corporation in Ottawa is seeking a senior ASIC backend designer to drive physical design, floorplanning, and timing closure for high-performance networks. You will work with RTL teams to integrate analog blocks and optimize PPA while leveraging advanced EDA flows.

The role emphasizes scripting, formal verification, and STA analysis to ensure signoff-quality results on tight submicron nodes. A strong collaboration with tool vendors and cross-functional teams is essential.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field with significant backend ASIC experience.
• Experience with submicron backend ASIC flow, timing/power/area trade-offs.
• Proven experience with Place&Route tools and script automation.
• Familiarity with UPF and SOCV/POCV concepts.

Responsibilities

• Define physical architecture and floorplans to enable timing closure and PPA balance.
• Collaborate with RTL designers to integrate digital and analog blocks.
• Tune EDA tool settings for signoff-quality results.
• Develop and run timing ECOs and functional ECOs as needed.
• Utilize Formality or Conformal for formal verification and analyze reports.
• Create productivity scripts for backend engineers and arbitrate tool workflows.
• Produce concise development status reports and identify optimization opportunities.
• Address timing challenges with DFT-related scan chain changes and CTS constraints.
• Perform STA, review timing reports, and debug P&R to STA correlations.

Skills

Place&Route tools

Scripting automation

STA

Timing closure

DFT/scan chain CTS

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Calibre

Formality

Conformal

UPF/SOCV/POCV concepts

Job description

Ciena Corporation in Ottawa is seeking a senior ASIC backend designer to drive physical design, floorplanning, and timing closure for high-performance networks. You will work with RTL teams to integrate analog blocks and optimize PPA while leveraging advanced EDA flows.

The role emphasizes scripting, formal verification, and STA analysis to ensure signoff-quality results on tight submicron nodes. A strong collaboration with tool vendors and cross-functional teams is essential.