Mixed-Signal IP Integration Engineer - Flexible ASIC

Ciena; Ottawa; On-site; CAD 75,000 - 120,000; Full time

Job summary

Ciena leads in high-speed connectivity and is hiring for a mixed-signal IC design role in Ottawa. You will work on custom macros within an ASIC flow, contributing to analog-digital timing handoff and IP integration in a collaborative engineering environment.

The position requires a degree in electrical or computing engineering and hands-on experience with Cadence tools, Verilog/RTL, place-and-route, and timing analysis. Strong communication and Linux/Windows fluency are valued.

Qualifications

• Bachelor’s or Master’s degree in electrical or computing engineering.
• Internship/co-op or applied project experience in a related field.
• Knowledge of analog design principles, schematic capture, layout, and analog simulation.
• Experience with Cadence tool suite and RTL/digital design concepts.

Responsibilities

• Solve engineering design challenges using electronics, math, and VLSI techniques.
• Generate mixed-signal representations for the digital design team (Verilog, Liberty, SPICE nets).
• Support macro-level standard cell interface placement for timing handoff and analysis.
• Contribute to digital IC design using standard cells and test-solutions models.

Skills

Verilog/RTL

Place-and-route

Static timing analysis

LVS / SPICE

Cadence tools

Education

Bachelor’s or Master’s degree in electrical or computing engineering

Tools

Cadence Design Systems

Cadence Innovus

Synopsys ICC II

Job description

Ciena leads in high-speed connectivity and is hiring for a mixed-signal IC design role in Ottawa. You will work on custom macros within an ASIC flow, contributing to analog-digital timing handoff and IP integration in a collaborative engineering environment.

The position requires a degree in electrical or computing engineering and hands-on experience with Cadence tools, Verilog/RTL, place-and-route, and timing analysis. Strong communication and Linux/Windows fluency are valued.