Senior ASIC Design Engineer - High-Speed DSP & Optical

Celero Communications, Inc.; Ottawa; Presencial; CAD 150.000 - 230.000; Jornada completa

Descripción de la vacante

Celero Communications, Inc. in Ottawa is seeking an experienced ASIC Design Engineer to contribute to high‑speed optical communication ASICs.

You will design digital blocks in Verilog/SystemVerilog, integrate DSP, SerDes, and mixed‑signal components, and collaborate across Analog, Verification, and Physical Design to deliver silicon through tapeout. You will perform synthesis, timing analysis, CDC, and lint, drive PPA optimizations, write automation in Python or Tcl, and guide other engineers in

Formación

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of experience in digital ASIC design with ownership of complex blocks.
• Strong proficiency in Verilog and SystemVerilog.
• Hands-on experience with ASIC design flows and EDA tools.
• Knowledge of DSP, SerDes, analog/mixed-signal ICs, and digital communications.
• Experience with synthesis, timing analysis, lint, CDC, formal verification, and RTL simulation.
• Familiarity with UVM or formal verification methods.
• Strong problem-solving and teamwork in a fast-paced startup.

Responsabilidades

• Design and implement high-performance digital circuits and ASIC blocks in Verilog/SystemVerilog.
• Integrate DSP, digital comms, and high-speed SerDes into complex ASICs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, PD, and Systems teams.
• Develop high-speed data paths, signal processing blocks, control logic, and interfaces for optical systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to ensure functionality.
• Contribute to block/top-level integration, verification, and silicon bring-up.
• Participate in architecture/design reviews and guide other engineers.
• Develop scripts in Python/Tcl to improve design/verification efficiency.
• Contribute to ASIC development from architecture through tapeout and silicon validation.

Conocimientos

Verilog/SystemVerilog

DSP

SerDes

Digital communications

RTL design

PPA optimization

Educación

Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related field

Herramientas

EDA tools

Descripción del empleo

Celero Communications, Inc. in Ottawa is seeking an experienced ASIC Design Engineer to contribute to high‑speed optical communication ASICs.

You will design digital blocks in Verilog/SystemVerilog, integrate DSP, SerDes, and mixed‑signal components, and collaborate across Analog, Verification, and Physical Design to deliver silicon through tapeout. You will perform synthesis, timing analysis, CDC, and lint, drive PPA optimizations, write automation in Python or Tcl, and guide other engineers in