Mixed-Signal IP Integration Engineer: High-Speed ASICs

Ciena Corporation; Ottawa; On-site; CAD 75,000 - 120,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

401K / DCPP with company matching

ESPP (Employee Stock Purchase Program)

EAP (Employee Assistance Program)

Company-paid holidays

Paid vacation

Job summary

Ciena Corporation in Ottawa is seeking a hardware-focused ASIC design engineer to design mixed-signal macros within an ASIC flow for high-baud-rate optical modems.

You will generate Verilog, SPICE netlists, and provide IP integration support, using Cadence and Synopsys tools. This role emphasizes analog/digital timing handoff and test methodologies.

The team collaborates across analog and digital disciplines, applying rigorous design and verification practices.

Qualifications

• Bachelor’s or master’s degree in electrical or computing engineering.
• Prior internship, co-op, or project experience relevant to the role.
• Analog design principles and experience with schematic capture, layout, extraction, pre- and post-layout analog simulation, DRC, and LVS.
• Fully conversant with Cadence Design Systems tools (Cadence)
• Solid understanding of digital design, including Verilog/RTL, place-and-route, and static timing analysis.
• Prior experience with Cadence Innovus or Synopsys Integrated Circuit Compiler II.

Responsibilities

• Develop representations of mixed-signal blocks for the digital design team.
• Produce Verilog, Liberty timing files, SPICE netlists, and layout/documents for IP integration.
• Develop design-for-test solutions and models aligned with ASIC test methodologies.
• Contribute to digital–analog timing handoff and place-and-route activities.

Skills

Verilog RTL

Digital design

Place-and-route

Static timing analysis

Schematic capture

Layout

LVS/DRC verification

Cadence tools

Verilog

Education

Bachelor’s degree in Electrical Engineering or Computing Engineering

Master’s degree in Electrical Engineering or Computing Engineering

Tools

Cadence Design Systems

Cadence Innovus

Synopsys ICC II

Job description

Ciena Corporation in Ottawa is seeking a hardware-focused ASIC design engineer to design mixed-signal macros within an ASIC flow for high-baud-rate optical modems.

You will generate Verilog, SPICE netlists, and provide IP integration support, using Cadence and Synopsys tools. This role emphasizes analog/digital timing handoff and test methodologies.

The team collaborates across analog and digital disciplines, applying rigorous design and verification practices.