Senior Physical Design Engineer

Ciena Corporation; Ottawa; Sur place; CAD 109 000 - 174 000; Plein temps

Avantages offerts par ce poste

Medical, dental, and vision plans

Employee Stock Purchase Program (ESPP)

401(K) / DCPP with company matching

Holidays

Paid sick leave

Vacation time

Résumé du poste

Ciena Corporation in Ottawa is seeking a senior ASIC backend designer to drive physical design, floorplanning, and timing closure for high-performance networks. You will work with RTL teams to integrate analog blocks and optimize PPA while leveraging advanced EDA flows.

The role emphasizes scripting, formal verification, and STA analysis to ensure signoff-quality results on tight submicron nodes. A strong collaboration with tool vendors and cross-functional teams is essential.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field with significant backend ASIC experience.
• Experience with submicron backend ASIC flow, timing/power/area trade-offs.
• Proven experience with Place&Route tools and script automation.
• Familiarity with UPF and SOCV/POCV concepts.

Responsabilités

• Define physical architecture and floorplans to enable timing closure and PPA balance.
• Collaborate with RTL designers to integrate digital and analog blocks.
• Tune EDA tool settings for signoff-quality results.
• Develop and run timing ECOs and functional ECOs as needed.
• Utilize Formality or Conformal for formal verification and analyze reports.
• Create productivity scripts for backend engineers and arbitrate tool workflows.
• Produce concise development status reports and identify optimization opportunities.
• Address timing challenges with DFT-related scan chain changes and CTS constraints.
• Perform STA, review timing reports, and debug P&R to STA correlations.

Connaissances

Place&Route tools

Scripting automation

STA

Timing closure

DFT/scan chain CTS

Formation

Bachelor’s degree in Electrical or Computer Engineering

Outils

Calibre

Formality

Conformal

UPF/SOCV/POCV concepts

Description du poste

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. Ciena’s WaveLogic family of products is a cornerstone of our optical fiber transmission solutions, driving innovation and success in the telecommunications industry.

Responsibilities

• Scope and define the physical architecture of designs, utilizing EDA vendor tools to build, adapt, and maintain a robust flow from netlist to full closure and GDSII generation.
• Partner with RTL circuit designers and other layout engineers to create optimal floorplans, design power grids, and clock distribution networks that achieve the best performance and power efficiency.
• Navigate and fine-tune EDA tool settings, parameters, and attributes to ensure signoff-quality results with an optimal balance of performance, power, and area (PPA).
• Identify and propose alternative implementations, trade-offs, and solutions to achieve lower power consumption and higher performance.
• Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design.
• Conduct initial Place & Route trials to refine design and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.
• Generate and implement timing ECOs to achieve timing closure, as well as functional ECOs to address RTL feature fixes when necessary.
• Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity.
• Write scripts to enhance productivity and efficiency for yourself and other backend engineers.
• Collaborate with tool and technology vendors to drive fixes, improve workflows, and evaluate new tools and features.
• Produce concise status reports at various stages of development, highlighting trade-offs and providing actionable insights.
• Resolve timing challenges associated with DFT through scan chain reordering, placement, and CTS constraints.
• Run Static Timing Analysis (STA), analyze timing reports, and debug issues related to timing constraints and correlation between P&R and STA tools.

Required Qualifications

• Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure
• Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade-offs.
• Proven experience working with Place&Route tools.
• Practical experience developing scripts to automate tasks throughout the backend flow.
• Understanding of UPF and SOCV/POCV concepts

Preferred Qualifications

• Experience in working with multiple power domains
• Experience with physical verification (Calibre).
• Experience with power integrity (EMIR)
• Hand-on experience creating and validating timing constraints
• Experience with Static Timing Analysis (STA)
• Experience with physical synthesis and full RTL-to-GDS flow using industry-standard EDA tools

Salary

Salary Range: The salary range for this role in Ottawa is $109, 000 - $174, 000

Benefits

• medical, dental, and vision plans
• participation in 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation time
• We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

Equal Opportunity

We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Company Culture

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