Frontend ASIC Synthesis & Timing Engineer

Ciena; Canada; On-site; CAD 71,000 - 113,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) (USA) & DCPP (Canada) matching

Employee Stock Purchase Program (ESPP)

Paid holidays, sick leave, andVacation

Job summary

Ciena, the global leader in high-speed connectivity, seeks a frontend engineer to implement ASIC frontend subsystems and optimize timing workflows across synthesis, clock domain crossing, and RTL verification in Canada.

You will collaborate with ASIC integration, IP development, physical design, and external EDA partners to align frontend and backend activities, influence design choices, and ensure on-time delivery in a dynamic environment.

Qualifications

• B.Sc. in Electrical Engineering, Computer Engineering, or related discipline (or equivalent experience).
• Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation.
• Familiarity with RTL design principles and hardware description languages.
• Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules.

Responsibilities

• Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
• Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
• Perform logical equivalence verification between RTL and gatelevel netlists throughout pre and postlayout stages
• Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity
• Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows
• Implement ECOs to support iterative design refinement
• Collaborate with ASIC integration, IP development, physical design, and external EDA partners to align frontend and backend activities

Skills

RTL design principles

Scripting (Python, Tcl)

multidisciplinary teamwork

deliverables to schedules

Education

B.Sc. in Electrical Engineering or Computer Engineering or related discipline

Tools

EDA tools

Design for Testability (DFT)

Job description

Ciena, the global leader in high-speed connectivity, seeks a frontend engineer to implement ASIC frontend subsystems and optimize timing workflows across synthesis, clock domain crossing, and RTL verification in Canada.

You will collaborate with ASIC integration, IP development, physical design, and external EDA partners to align frontend and backend activities, influence design choices, and ensure on-time delivery in a dynamic environment.