New Grad: Mixed-Signal IP Integration Engineer

Ciena Corporation; Ottawa; Hybrid; CAD 75,000 - 120,000; Full time

Job summary

Ciena Corporation in Ottawa, Ontario, is seeking a Mixed-Signal IP Integration Engineer - New Grad to join our team and contribute to the design and integration of mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.

The role involves working with Verilog/RTL, SPICE, and Cadence tools, aiding analog-digital timing handoff and static timing analysis, and collaborating across design teams. Prior internship or co-op in IC design is valued.

Qualifications

• Bachelor's or master's in electrical or computing engineering.
• Internship/co-op or project experience in IC design.
• Analog design principles and schematic/layout experience.
• Proficiency with Cadence tools (Innovus, etc.).
• Strong digital design with Verilog/RTL and STA.
• Experience with layout vs. schematic verification and LVS.
• Proficiency in Windows and Linux.

Responsibilities

• Generate representations of mixed-signal blocks for the digital design team (Verilog, LIB, Liberty, SPICE).
• Assist in design and place-and-route of macro-level interfaces for timing handoff and STAs.
• Contribute to digital IC design using standard cells and develop DFT models.
• Create SPICE netlists for chip-level LVS and layout verification.

Skills

VLSI design

Verilog/RTL

Analog design

Digital design

Cadence tools

Cadence Innovus

Synopsys IC Compiler II

Python scripting

Linux/Windows

Schematic capture

Layout

Education

Bachelor's or Master’s in Electrical Engineering or Computing Engineering

Tools

Cadence Innovus

Synopsys IC Compiler II

Cadence Design Systems

Job description

Ciena Corporation in Ottawa, Ontario, is seeking a Mixed-Signal IP Integration Engineer - New Grad to join our team and contribute to the design and integration of mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.

The role involves working with Verilog/RTL, SPICE, and Cadence tools, aiding analog-digital timing handoff and static timing analysis, and collaborating across design teams. Prior internship or co-op in IC design is valued.