Mixed Signal IP Integration Engineer – New Grad

Ciena Corporation; Ottawa; Hybrid; CAD 75,000 - 120,000; Full time

Job summary

Ciena Corporation in Ottawa, Ontario, is seeking a Mixed-Signal IP Integration Engineer - New Grad to join our team and contribute to the design and integration of mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems.

The role involves working with Verilog/RTL, SPICE, and Cadence tools, aiding analog-digital timing handoff and static timing analysis, and collaborating across design teams. Prior internship or co-op in IC design is valued.

Qualifications

• Bachelor's or master's in electrical or computing engineering.
• Internship/co-op or project experience in IC design.
• Analog design principles and schematic/layout experience.
• Proficiency with Cadence tools (Innovus, etc.).
• Strong digital design with Verilog/RTL and STA.
• Experience with layout vs. schematic verification and LVS.
• Proficiency in Windows and Linux.

Responsibilities

• Generate representations of mixed-signal blocks for the digital design team (Verilog, LIB, Liberty, SPICE).
• Assist in design and place-and-route of macro-level interfaces for timing handoff and STAs.
• Contribute to digital IC design using standard cells and develop DFT models.
• Create SPICE netlists for chip-level LVS and layout verification.

Skills

VLSI design

Verilog/RTL

Analog design

Digital design

Cadence tools

Cadence Innovus

Synopsys IC Compiler II

Python scripting

Linux/Windows

Schematic capture

Layout

Education

Bachelor's or Master’s in Electrical Engineering or Computing Engineering

Tools

Cadence Innovus

Synopsys IC Compiler II

Cadence Design Systems

Job description

They gather information about your interactions on the site, such as which pages you visit frequently, how long you stay, and the links or buttons you click. They help us record any difficulties you have with the website and help us to evaluate the effectiveness of our advertising. By analyzing this data, we can understand what aspects of our site are effective and identify areas for improvement.* This is a secondary processing purpose.* This is a secondary processing purpose.* This is a primary processing purpose.* This is a secondary processing purpose.Mixed Signal IP Integration Engineer - New Grad page is loaded## Mixed Signal IP Integration Engineer - New Gradlocations: Ottawatime type: Full timeposted on: Publié aujourd'huijob requisition id: R031688As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We're a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being - on and off the job. Connect with a career that matters.Join a team focused on the design and integration of custom mixed-signal macros within an ASIC flow for next-generation high-baud-rate optical modems. Work involves advanced nanoscale CMOS technologies that enable high-performance optical and electrical interfaces. The role provides opportunities to contribute to mixed-signal circuit design and IP integration activities in a collaborative engineering environment.**How you will make an impact:*** Utilize knowledge of electronics, mathematics, VLSI design, and computer-aided design tools to solve engineering design challenges.* Generate representations of mixed-signal blocks for the digital design team, including Verilog, Library Exchange Format, Liberty timing files, documentation, preliminary and final layout files, and SPICE netlists for chip-level LVS as part of IP integration activities.* Develop understanding of the design and place-and-route of macro-level standard cell interfaces to facilitate analog-digital timing handoff and static timing analysis.* Contribute to digital integrated circuit design using standard cell libraries and develop design-for-test solutions and models aligned with ASIC test methodologies.**The must haves:*** Education: Completed a bachelor's or master's degree in electrical or computing engineering.* Experience: Previous internship, co-op, or applied project experience relevant to the role.* Analog design principles and experience with schematic capture, layout, extraction, pre- and post-layout analog simulation, design rule checking, and layout versus schematic verification.* Fully conversant with the custom IC tools from Cadence Design Systems.* A solid understanding of digital design, including Verilog/RTL, place-and-route, and static timing analysis.* Prior experience with Cadence Innovus or Synopsys Integrated Circuit Compiler II.**Nice to haves:*** Scripting in Python and Cadence Skill language* Excellent oral and written communication skills* Confident working in both Windows and Linux environments**Pay range:**The salary range for this role is 75,100.00 - 119,900.00Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.Ciena is an Equal Opportunity Employer, including disability and protected veteran status.If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.### Our workplace experienceWe prioritize growth, wellbeing, and recognition for our teams. about how we work together, support one another, and reward our people.