ASIC Automation Intern for Next-Gen DSP & Verification

Ciena Corporation; Ottawa; Hybrid; CAD 73,068,000 - 100,289,000; Full time

Benefits offered by this job

Employee Assistance Program

Paid holidays

Paid sick leave

Vacation pay

Job summary

Ciena Corporation in Ottawa is seeking an ASIC Engineer Intern to support automation infrastructure for next‑generation ASIC devices. You will work with the design, layout, integration, and verification teams on DSP ASIC development for optical communications.

The role offers exposure to SystemVerilog/UVM verification, Python-based tooling, and Linux environments, with mentorship and a 4–8 month term starting January 2027. Paid internship with competitive benefits and holidays.

Qualifications

• Programming experience using Java, Python, TCL, or SystemVerilog.
• Familiarity with Linux-based development environments.
• Ability to work in Agile, with JIRA/Confluence in a team.
• Nice to have prior ASIC/FPGA development exposure.

Responsibilities

• Contribute to automation infrastructure for ASIC devices.
• Collaborate with developers to advance ASIC design, layout, integration, and verification.
• Develop design blocks and evaluate performance and correctness.
• Create constraints and automate ASIC integration processes.
• Develop verification components in SystemVerilog/UVM and enhance Python-based workflows.

Skills

Java

Python

TCL

SystemVerilog

Linux

Tools

Git

JIRA

Confluence

Job description

Ciena Corporation in Ottawa is seeking an ASIC Engineer Intern to support automation infrastructure for next‑generation ASIC devices. You will work with the design, layout, integration, and verification teams on DSP ASIC development for optical communications.

The role offers exposure to SystemVerilog/UVM verification, Python-based tooling, and Linux environments, with mentorship and a 4–8 month term starting January 2027. Paid internship with competitive benefits and holidays.