Optical DSP & Mixed-Signal ASIC Design Engineer

Celero Communications, Inc.; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Celero Communications, Inc. is seeking an ASIC Design Engineer to join our fast-growing Ottawa team. You will design high-performance digital ASICs for optical communication systems, using Verilog/SystemVerilog and collaborating with DSP, SerDes, and analog teams.

You will drive from architecture through tapeout, perform synthesis and timing analyses, optimize for PPA, and develop automation scripts in Python/Tcl to streamline design flows in a startup environment.

Qualifications

• 5+ years of experience in digital ASIC design with ownership of complex blocks.
• Strong proficiency in Verilog and SystemVerilog.
• Experience with ASIC design flows and EDA tools.
• Ability to work with DSP, SerDes, analog interfaces and mixed-signal blocks.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop DSP, digital comms, and high-speed SerDes functionality into complex ASICs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, and Physical Design teams.
• Design data paths, signal processing blocks, and interfaces for optical comms.
• Perform synthesis, timing analysis, lint, CDC, and signoff activities.
• Optimize for performance, power, and area (PPA) and perform RTL simulation.

Skills

Verilog/SystemVerilog

Digital ASIC design

DSP

High-speed SerDes

Analog/Mixed-Signal ICs

Digital communications

Optical communications

Python/Tcl scripting

Education

Bachelor’s or higher in Electrical Engineering, Computer Engineering, or related field

Job description

Celero Communications, Inc. is seeking an ASIC Design Engineer to join our fast-growing Ottawa team. You will design high-performance digital ASICs for optical communication systems, using Verilog/SystemVerilog and collaborating with DSP, SerDes, and analog teams.

You will drive from architecture through tapeout, perform synthesis and timing analyses, optimize for PPA, and develop automation scripts in Python/Tcl to streamline design flows in a startup environment.