I/O Chiplet RTL Design Lead for High-Speed Interconnects

BTA Design Services Inc.; Ottawa; Hybrid; CAD 120,000 - 170,000; Full time

Job summary

BTA Design Services Inc. in Ottawa, Canada, is seeking a Senior I/O Chiplet RTL Design Engineer.

You will translate architectural requirements into synthesizable SystemVerilog/Verilog and own blocks from spec to front-end sign-off, integrating third-party IP while balancing power, performance and area. The role requires extensive ASIC RTL experience, strong SystemVerilog/Verilog, and expertise with high-speed interfaces like PCIe and Ethernet.

Qualifications

• Extensive hands-on ASIC RTL design experience with ownership through tape-out.
• Strong SystemVerilog and Verilog skills, translating specs into maintainable RTL.
• Deep knowledge of high-bandwidth datapaths, pipelining, and multi-clock design.
• Experience integrating IP and high-speed interfaces such as PCIe, Ethernet, or die-to-die interconnect.
• Knowledge of CDC/RDC, reset sequencing, assertions, and static checks.
• Synthesis, timing constraints, and timing-report analysis; coord with physical design.
• Python, Tcl or similar scripting to automate design flows.
• Ability to lead technical decisions, reviews and communicate risks.

Responsibilities

• Define block micro-architecture, interfaces, and latency/throughput budgets.
• Develop configurable static-switch fabrics, protocol multiplexers, datapaths, and PD logic.
• Configure and integrate protocol and PHY IP with clocking and control interfaces.
• Implement CSR, configuration sequencing, interrupts, and management logic with firmware.
• Write assertions and resolve lint/CDC/RDC/connectivity findings.
• Develop timing constraints and collaborate on partitioning and timing closure.
• Implement low-power controls and work with DFT & formal equivalence.
• Debug with verification engineers and deliver RTL/synthesis handoffs.

Skills

ASIC RTL design

SystemVerilog

Verilog

Datapath design

IP integration

Python/Tcl scripting

Leadership & reviews

Timing closure

Multi-clock design

Tools

Python

Tcl

Job description

BTA Design Services Inc. in Ottawa, Canada, is seeking a Senior I/O Chiplet RTL Design Engineer.

You will translate architectural requirements into synthesizable SystemVerilog/Verilog and own blocks from spec to front-end sign-off, integrating third-party IP while balancing power, performance and area. The role requires extensive ASIC RTL experience, strong SystemVerilog/Verilog, and expertise with high-speed interfaces like PCIe and Ethernet.