Senior I/O Chiplet RTL Design Engineer

BTA Design Services; Ottawa; Hybrid; CAD 130,000 - 170,000; Full time

Job summary

BTA Design Services in Ottawa, Canada, is seeking a Senior I/O Chiplet RTL Design Engineer to translate architectural requirements into synthesizable SystemVerilog and Verilog, owning blocks from specification through front-end sign-off.

You will integrate protocol and PHY IP, manage power, performance, and area, and collaborate with architecture, verification, firmware, and physical design teams throughout the design lifecycle.

Qualifications

• Extensive hands-on ASIC RTL design experience with ownership through tape-out.
• Strong SystemVerilog/Verilog skills and translating specs into maintainable RTL.
• Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design.
• Experience integrating complex IP and high-speed interfaces (PCIe, Ethernet, die-to-die).
• Knowledge of CDC/RDC, reset sequencing, assertions, and static checks.
• Synthesis, timing constraints, timing-report analysis, and working with physical design.
• Proficient in Python or Tcl for automation of design flows.
• Ability to lead design reviews and communicate risks and progress clearly.

Responsibilities

• Define block micro-architecture, interface specs, and latency/throughput budgets.
• Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths.
• Configure and integrate protocol/PHY IP, including clocking and interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management logic with firmware.
• Write assertions and resolve lint, CDC, RDC, and connectivity findings.
• Develop timing constraints, analyze synthesis results, coordinate with physical design.
• Implement low-power controls and power-intent checks, DFT, and formal equivalence.
• Debug failures with verification engineers and deliver RTL/synthesis handoffs.

Skills

ASIC RTL design

SystemVerilog/Verilog

High-bandwidth datapaths

Multi-clock design

IP integration

CDC/RDC

Timing constraints

Scripting: Python/Tcl

Design reviews leadership

Static design checks

Tools

Synthesis tools

Static timing analysis

Job description

About BTADesignServices

Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production-ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching for aSenior I/O Chiplet RTL Design Engineer.

About the Engagement

The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed programspecifications are shared under confidentiality during interviews.

About the Position

You will translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assignedblocks from specification through front-end sign-off. The role combines custom datapath and control logicwith integration of third-party protocol and PHY IP, with close attention to power, performance, area, andphysical implementation.

Key Responsibilities

• Define block micro-architecture, interface specifications, and measurable latency, throughput, andresource budgets.
• Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundaryrate-adaptation logic.
• Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management logic alongside thefirmware team.
• Write assertions and resolve lint, clock-domain crossing (CDC), reset-domain crossing (RDC), andconnectivity findings.
• Develop timing constraints, analyze synthesis results, and work with physical design on partitioning,congestion, and timing closure.
• Implement low-power controls and support power-intent checks, DFT integration, and formalequivalence activities.
• Debug failures with verification engineers, maintain design documentation, and deliver reviewed RTLand synthesis handoffs.

Must-Have Qualifications

• Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successfultape-out.
• Strong SystemVerilog and Verilog skills and experience translating specifications into clear, maintainableRTL.
• Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design.
• Practical experience integrating complex IP and working with at least one high-speed interface such asPCIe, Ethernet, or die-to-die interconnect.
• Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks.
• Hands-on synthesis, timing constraints, and timing-report analysis; ability to resolve issues with physicaldesign.
• Scripting skills in Python, Tcl, or similar languages to automate design flows.
• Ability to own technical decisions, lead design reviews, and communicate risks and progress clearly.

Nice-to-Have

• UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advancedpackaging constraints.
• PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience.
• Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning.
• Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototypingexperience.

Work Arrangement

Ottawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and projectneeds. Clear written communication, independent execution, and collaboration with distributed engineeringteams are essential.

Compensation

Compensation will reflect individual experience, technical capability, and the responsibilities of the role. Thepackage will be discussed during the recruitment process.

Why Work With Us

Join an experienced team working on the connectivity challenges behind advanced AI and computingsystems. You will have direct technical ownership, close access to architects and implementation specialists,and the opportunity to shape reusable engineering methods for future chiplet programs. We value soundengineering judgment, collaboration, and a sustainable balance between demanding work and life outside it.

Only candidates selected for an interview will be contacted.

DISCLAIMER

BTA Design Services is an equal opportunity employer. We welcome applications from candidates of all backgrounds and are committed to an inclusive,accessible recruitment process. Accommodations are available on request at any stage of hiring.

This posting is for recruitment purposes only and does not constitute an offer of employment or a contract. Role scope, requirements, and compensation aresubject to change. All applications are handled in confidence.