Senior ASIC RTL Design Engineer

USA Tech Recruit; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

USA Tech Recruit is seeking a Senior ASIC RTL Design Engineer to own blocks from architectural specs through front-end sign-off. You will work on an advanced I/O chiplet integrating die-to-die connectivity with multi-protocol, high-speed I/O, collaborating with architecture, RTL, verification, firmware, PD, and IP teams.

You’ll drive microarchitecture, clocking, and power/area optimization for demanding silicon, including protocol and PHY IP integration and timing closure in a collaborative

Qualifications

• 10+ years of hands-on ASIC RTL design experience.
• Strong expertise in SystemVerilog and Verilog, translating specs into RTL.
• Experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock designs.
• Practical IP integration with PCIe, Ethernet, or die-to-die interconnect.
• Strong CDC, RDC, reset sequencing, assertions and static design checks.
• Synthesis, timing constraints, and timing-report analysis experience.
• Collaboration with physical design teams to resolve timing and congestion.

Responsibilities

• Define block-level microarchitecture, interface specs, latency, throughput, and budgets.
• Translate requirements into synthesizable SystemVerilog/Verilog RTL.
• Develop configurable static-switch fabrics, protocol multiplexers, datapaths, and boundary rate-adaptation logic.
• Configure and integrate complex protocol and PHY IP, including clocking, reset, status, and control interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management with firmware teams.
• Develop assertions and resolve lint, CDC, RDC findings.
• Develop timing constraints, analyze synthesis results, and work with PD on partitioning and timing closure.
• Implement low-power controls and power-intent checks, DFT and formal equivalence.
• Debug design issues with verification, and lead design reviews.
• Deliver RTL and synthesis handoffs aligned with milestones and front-end sign-off requirements.

Skills

ASIC RTL design

SystemVerilog

Verilog

High-speed datapaths

IP integration

PCIe

Ethernet interconnect

CDC/RDC

Synthesis & timing

Python/Tcl scripting

Front-end sign-off

Multi-clock designs

Job description

A specialist engineering consultancy supporting advanced ASIC, FPGA, and embedded systems development is partnering with a global technology company developing high-performance silicon for next-generation connectivity and networking applications.

We are looking for a Senior ASIC RTL Design Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol, high-speed I/O. The technology brings together interfaces including UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.

You will work closely with architecture, RTL, verification, firmware, physical design, and IP teams, taking ownership of assigned design blocks from architectural specification through front-end sign-off. The role combines custom datapath and control logic with the integration of third-party protocol and PHY IP, with a strong emphasis on power, performance, area, and physical implementation.

Client identity and detailed programme specifications will be shared confidentially during the interview process.

Key Responsibilities:

• Define block-level microarchitecture, interface specifications, latency, throughput, and resource budgets.
• Translate architectural requirements into clean, synthesizable SystemVerilog and Verilog RTL.
• Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic.
• Configure and integrate complex protocol and PHY IP, including clocking, reset, status, and control interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management logic in collaboration with firmware teams.
• Develop assertions and resolve lint, CDC, RDC, and connectivity findings.
• Develop timing constraints, analyze synthesis results, and work closely with physical design teams on partitioning, congestion, and timing closure.
• Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities.
• Debug design issues in partnership with verification engineers and maintain clear, accurate technical documentation.
• Lead design reviews and communicate technical risks, challenges, dependencies, and progress clearly.
• Deliver reviewed RTL and synthesis handoffs aligned with project milestones and front-end sign-off requirements.

Key Qualifications:

• 10+ years of hands-on ASIC RTL design experience, including ownership of designs through successful tape-out.
• Strong expertise in SystemVerilog and Verilog, with a track record of translating specifications into maintainable, production-quality RTL.
• Strong experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock designs.
• Practical experience integrating complex IP and at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
• Strong understanding of CDC, RDC, reset sequencing, assertions, and static design checks.
• Hands-on experience with synthesis, timing constraints, and timing-report analysis.
• Experience working closely with physical design teams to resolve timing, congestion, and implementation challenges.
• Scripting experience with Python, Tcl, or similar languages for design-flow automation.
• Ability to take ownership of significant technical decisions, lead design reviews, and drive blocks through front-end sign-off.
• Strong communication skills and the ability to work effectively across architecture, verification, firmware, physical design, and IP teams.

Nice to Have:

• Experience with UCIe or other chiplet interconnect technologies, including protocol-to-PHY integration and advanced packaging considerations.
• Experience with PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration.
• Experience developing physically aware RTL partitions.
• Experience with embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping.

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.com/wp-content/uploads/2024/07/European-Tech-Recruit-Privacy-Notice-2024.pdf