Senior Chiplet Verification Engineer

European Recruitment BV; Ottawa; On-site; CAD 120,000 - 150,000; Full time

Job summary

European Recruitment BV is seeking a Senior Verification Engineer in Ottawa to lead verification efforts for advanced ASIC blocks and chip-level functions across North America.

You will develop verification plans, build reusable SystemVerilog/UVM testbenches, integrate VIPs, and collaborate with architecture, RTL, firmware and IP teams to deliver sign-off-ready silicon. The role covers high-speed datapaths and multi-clock domains, with ownership through tape-out.

Qualifications

• 10+ years of hands-on ASIC verification through tape-out and sign-off.
• Expertise in SystemVerilog and UVM with constrained-random stimulus.
• Experience with VIP integration and reference models.
• Strong regression automation and scripting skills.

Responsibilities

• Develop verification plans mapping requirements to test scenarios and sign-off criteria.
• Design and maintain SystemVerilog/UVM environments with sequences, agents, scoreboards, reference models, and assertions.
• Integrate VIP and models for end-to-end verification across interfaces.
• Verify CSR access, boot sequences, interrupts, and error-handling with firmware teams.
• Automate regressions, triage failures, and drive coverage to closure.
• Review CDC/RDC findings and support silicon bring-up.
• Report readiness and remaining risks to stakeholders.

Skills

SystemVerilog

UVM

Constrained-random testing

Testbench architecture

Debugging complex failures

Scripting

Automation

Multi-clock & reset behavior

VIP integration

Silicon bring-up

Job description

Our client, a North American ASIC Services provider is looking for experienced Verification engineers to join their growing team in Ottawa to work on various Design projects for semiconductor clients across North America.

The I/O chiplet connects die-to-die interfaces with multi-protocol, high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.

You will collaborate closely with architecture, RTL, verification, firmware, physical design, and IP teams to deliver complex silicon solutions.

Client identity and detailed programme specifications will be shared confidentially during the interview process.

About the Position

You will establish and execute verification plans for assigned blocks, subsystems, and chip-level functions. Working closely with designers and architects, you will translate requirements into measurable verification goals and deliver the evidence required for sign-off.

The role covers both high-speed datapaths and firmware-controlled management functions, with ownership extending through verification closure and tape-out.

Key Responsibilities

• Develop verification plans that map requirements to test scenarios, platforms, coverage goals, and sign-off criteria.
• Design and maintain reusable SystemVerilog/UVM environments, including sequences, agents, scoreboards, reference models, and assertions.
• Integrate vendor VIP and models, verifying configured IP and end-to-end connectivity across protocol and PHY interfaces.
• Verify static-switch mappings, protocol modes, data integrity, latency, throughput, reset, and recovery behaviour.
• Verify CSR access, boot and configuration sequences, sideband management, interrupts, and error-handling mechanisms in collaboration with firmware teams.
• Apply simulation, formal verification, connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.
• Automate regressions, triage failures, and drive functional, assertion, and code coverage to closure, including documented exclusions.
• Review CDC/RDC findings with designers and support gate-level sanity checks and silicon bring-up.
• Report verification readiness, remaining risks, and sign-off evidence clearly to relevant stakeholders.

Must-Have Qualifications

• 10+ years of hands-on ASIC verification experience, with ownership through tape-out and sign-off.
• Strong SystemVerilog and UVM expertise, including constrained-random stimulus and reusable testbench architecture.
• Proven experience developing verification plans, defining coverage, debugging complex failures, and driving verification closure.
• Experience verifying high-speed interfaces, complex SoCs, networking ASICs, or die-to-die interconnects.
• Hands-on experience with VIP integration, reference modelling, scoreboarding, and assertion-based verification.
• Strong understanding of multi-clock and reset behaviour, protocol corner cases, and the limitations of simulation and static verification.
• Strong scripting and regression automation skills, with disciplined test and configuration management practices.
• Ability to work independently, review others' work, and clearly communicate remaining risks and sign-off evidence.

Nice-to-Have Experience

• Experience with UCIe, PCIe Gen6/Gen7, Ethernet PCS/FEC, 224G SerDes, or mixed-signal IP verification.
• Formal model checking, connectivity verification
• Embedded processor verification, secure boot, AXI/APB, register models, or firmware-driven testing.
• FPGA prototyping or emulation and silicon bring-up experience.
• Experience with reviewed and controlled AI-assisted verification workflows.