Senior ASIC RTL Design Lead in High-Speed I/O and Chiplets

USA Tech Recruit; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

USA Tech Recruit is seeking a Senior ASIC RTL Design Engineer to own blocks from architectural specs through front-end sign-off. You will work on an advanced I/O chiplet integrating die-to-die connectivity with multi-protocol, high-speed I/O, collaborating with architecture, RTL, verification, firmware, PD, and IP teams.

You’ll drive microarchitecture, clocking, and power/area optimization for demanding silicon, including protocol and PHY IP integration and timing closure in a collaborative

Qualifications

• 10+ years of hands-on ASIC RTL design experience.
• Strong expertise in SystemVerilog and Verilog, translating specs into RTL.
• Experience with high-bandwidth datapaths, pipelining, multiplexing, and multi-clock designs.
• Practical IP integration with PCIe, Ethernet, or die-to-die interconnect.
• Strong CDC, RDC, reset sequencing, assertions and static design checks.
• Synthesis, timing constraints, and timing-report analysis experience.
• Collaboration with physical design teams to resolve timing and congestion.

Responsibilities

• Define block-level microarchitecture, interface specs, latency, throughput, and budgets.
• Translate requirements into synthesizable SystemVerilog/Verilog RTL.
• Develop configurable static-switch fabrics, protocol multiplexers, datapaths, and boundary rate-adaptation logic.
• Configure and integrate complex protocol and PHY IP, including clocking, reset, status, and control interfaces.
• Implement CSR access, configuration sequencing, interrupts, and management with firmware teams.
• Develop assertions and resolve lint, CDC, RDC findings.
• Develop timing constraints, analyze synthesis results, and work with PD on partitioning and timing closure.
• Implement low-power controls and power-intent checks, DFT and formal equivalence.
• Debug design issues with verification, and lead design reviews.
• Deliver RTL and synthesis handoffs aligned with milestones and front-end sign-off requirements.

Skills

ASIC RTL design

SystemVerilog

Verilog

High-speed datapaths

IP integration

PCIe

Ethernet interconnect

CDC/RDC

Synthesis & timing

Python/Tcl scripting

Front-end sign-off

Multi-clock designs

Job description

USA Tech Recruit is seeking a Senior ASIC RTL Design Engineer to own blocks from architectural specs through front-end sign-off. You will work on an advanced I/O chiplet integrating die-to-die connectivity with multi-protocol, high-speed I/O, collaborating with architecture, RTL, verification, firmware, PD, and IP teams.

You’ll drive microarchitecture, clocking, and power/area optimization for demanding silicon, including protocol and PHY IP integration and timing closure in a collaborative