Senior ASIC RTL Architect for High-Performance IP

European Recruitment BV; Ottawa; On-site; CAD 120,000 - 160,000; Full time

Job summary

European Recruitment BV is seeking experienced Verification engineers in Ottawa to work on leading-edge ASIC projects for North American clients. You will translate architectural requirements into synthesizable SystemVerilog/Verilog, owning blocks from spec through front-end sign-off, with a focus on power, performance and physical implementation.

You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones with

Qualifications

• 10+ years hands-on ASIC RTL design experience
• Strong SystemVerilog and Verilog skills; translate specs into RTL
• Experience with high-bandwidth datapaths, pipelining and multi-clock design
• Experience integrating complex IP + high-speed interfaces (PCIe, Ethernet, die-to-die)
• Strong CDC/RDC, reset sequencing, assertions, and static checks
• Synthesis, timing constraints, timing-report analysis; coordinate with physical design
• Scripting in Python/Tcl to automate design flows
• Ability to own technical decisions, lead reviews, communicate risks clearly

Responsibilities

• Define block microarchitecture, interfaces, and latency/performance budgets
• Develop configurable static-switch fabrics, protocol multiplexers, datapaths
• Integrate protocol and PHY IP including clocking, reset, status interfaces
• Implement CSR access, configuration sequencing, interrupts with firmware
• Develop assertions and resolve lint, CDC, RDC findings
• Create timing constraints, analyse synthesis results with PD teams on timing closure
• Implement low-power controls, UPF usage, and DFT integration
• Collaborate with verification to debug design issues and document work clearly
• Deliver RTL and synthesis handoffs aligned with milestones

Skills

ASIC RTL design

SystemVerilog/Verilog

High-speed interfaces

CDC/RDC/Assertions

Synthesis & timing

Scripting (Python/Tcl)

Technical leadership/ownership

Tools

Python

Tcl

Job description

European Recruitment BV is seeking experienced Verification engineers in Ottawa to work on leading-edge ASIC projects for North American clients. You will translate architectural requirements into synthesizable SystemVerilog/Verilog, owning blocks from spec through front-end sign-off, with a focus on power, performance and physical implementation.

You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones with