Senior I/O Chiplet Verification Engineer

BTA Design Services; Ottawa; Hybrid; CAD 150,000 - 190,000; Full time

Job summary

BTA Design Services in Ottawa, Canada, seeks a Senior I/O Chiplet Verification Engineer to own verification plans for high-speed datapaths and firmware‑controlled management functions. You will collaborate across architecture, RTL, verification, firmware, physical design and IP partners, turning requirements into measurable goals and providing sign-off evidence.

Hybrid Ottawa-based role with strong scripting, testbench development, and a focus on high-speed interfaces and clock-domain

Qualifications

• Extensive hands-on ASIC verification experience, 10+ years and tape-out ownership.
• Strong SystemVerilog and UVM skills with constrained-random stimulus.
• Ability to write verification plans, define coverage, debug complex failures.
• Experience verifying high-speed interfaces and die-to-die interconnects.
• VIP integration, reference modeling, scoreboarding, and assertions.
• Understanding multi-clock and reset behavior and simulation limits.
• Scripting and regression automation skills; disciplined configuration management.
• Ability to work independently and communicate risks clearly.

Responsibilities

• Build verification plans mapping requirements to test scenarios, platforms, coverage goals, and sign-off criteria.
• Develop reusable SystemVerilog/UVM environments, sequences, agents, scoreboards, reference models, and assertions.
• Integrate vendor VIP and models; verify configured IP and end-to-end connectivity across protocol and PHY interfaces.
• Verify CSR access, boot and configuration sequences, sideband management, interrupts, and error handling with firmware teams.
• Apply simulation, formal and connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.
• Automate regressions, triage failures, and close functional, assertion, and code coverage with documented exclusions.
• Review CDC/RDC findings with designers, support gate-level sanity checks and bring-up, and report verification readiness.
• Report verification readiness.

Skills

SystemVerilog

UVM

Constrained-random

Verification planning

VIP integration

Scoreboarding

Assertions

Scripting

Regression automation

Independent working

Job description

About BTADesignServices

Headquartered in Ottawa, BTA Design Services supports the electronic design community across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development. We strengthen our clients' engineering teams and accelerate the delivery of complete, production-ready designs.

We are adaptable, efficient, and built around exceptional technical talent. Our continued growth reflects the trust our clients place in us, and we are currently searching for aSenior I/O Chiplet Verification Engineer.

About the Engagement

The I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe,Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture,RTL, verification, firmware, physical design, and IP partners. Client identity and detailed programspecifications are shared under confidentiality during interviews.

About the Position

You will establish and execute verification plans for assigned blocks, subsystems, and chip-level functions.Working closely with designers and architects, you will turn requirements into measurable verification goalsand produce the evidence needed for sign-off, covering both high-speed datapaths and firmware-controlledmanagement functions.

Key Responsibilities

• Build verification plans that map requirements to test scenarios, platforms, coverage goals, and sign-offcriteria.
• Develop reusable SystemVerilog/UVM environments, sequences, agents, scoreboards, referencemodels, and assertions.
• Integrate vendor VIP and models; verify configured IP and end-to-end connectivity across protocol andPHY interfaces.
• Verify legal static-switch mappings, protocol modes, data integrity, latency, throughput, and reset orrecovery behavior.
• Verify CSR access, boot and configuration sequences, sideband management, interrupts, and errorhandling with firmware teams.
• Apply simulation, formal and connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.
• Automate regressions, triage failures, and close functional, assertion, and code coverage withdocumented exclusions.
• Review CDC/RDC findings with designers, support gate-level sanity checks and bring-up, and reportverification readiness.

Must-Have Qualifications

• Extensive hands-on ASIC verification experience, 10 years or more, with ownership through tape-outsign-of.
• Strong SystemVerilog and UVM skills, including constrained-random stimulus and reusable testbencharchitecture.
• Proven ability to write verification plans, define coverage, debug complex failures, and driveclosure.
• Experienceverifyinghigh-speedinterfaces,complexSoCs,networkingASICs,ordie-to-dieinterconnect.
• Hands‑onVIPintegration,referencemodeling,scoreboarding,andassertion-basedverification.
• Understanding of multi-clock and reset behavior, protocol corner cases, and the limits of simulation andstatic checks.
• Strong scripting and regression automation skills, with disciplined test and configuration management.
• Abilitytoworkindependently,reviewothers'work,andexplainremainingrisksandsign-offevidenceclearly.

Nice-to-Have

• UCIe,PCIeGen6/Gen7,EthernetPCS/FEC,or224GSerDesandmixed-signalIPverification.
• Formalmodelchecking,connectivityverification,orpower-awaresimulationwithUPF.
• Embeddedprocessorverification,secureboot,AXI/APB,registermodels,orfirmware-driventesting.
• FPGA prototyping or emulation, silicon bring-up, and reviewed AI-assisted verification workflows.

Work Arrangement

Ottawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and projectneeds. Clear written communication, independent execution, and collaboration with distributed engineeringteams are essential.

Compensation

Compensation will reflect individual experience, technical capability, and the responsibilities of the role. Thepackage will be discussed during the recruitment process.

Why Work With Us

Join an experienced team working on the connectivity challenges behind advanced AI and computingsystems. You will have direct technical ownership, close access to architects and implementation specialists,and the opportunity to shape reusable engineering methods for future chiplet programs. We value soundengineering judgment, collaboration, and a sustainable balance between demanding work and life outside it.

Onlycandidatesselectedforaninterviewwillbecontacted.

Disclaimer

BTA Design Services is an equal opportunity employer. We welcome applications from candidates of all backgrounds and are committed to an inclusive,accessible recruitment process. Accommodations are available on request at any stage of hiring. This posting is for recruitment purposes only and does not constitute an offer of employment or a contract. Role scope, requirements, and compensation are subject to change. All applications are handled in confidence.