Senior FPGA Design & Validation Lead

HCL Technologies Limited; Belgium; On-site; EUR 75,000 - 120,000; Full time

Job summary

HCL Technologies Limited in Belgium seeks a Senior Design Lead with 8–10 years of FPGA design and validation experience to drive complex FPGA projects from RTL to bit files and electrical validation. You will optimize timing constraints, address clock domain crossings, and collaborate with design teams while using Vivado and Synplify, Verilog/SystemVerilog, and Python for test development.

The role requires hands-on bench validation, debugging at device and board level, and experience with SVN

Qualifications

• Experience in FPGA flow from RTL to bit file generation and electrical validation.
• Strong grasp of timing constraints and timing reports in FPGA designs.
• Proven skills in digital design using VHDL/Verilog/SystemVerilog.
• Ability to adapt ASIC RTL to fit FPGA resources and constraints.

Responsibilities

• Lead FPGA design and validation activities with 8–10 years of experience.
• Develop timing constraints and analyze timing reports with the design team.
• Create and run C-based tests and Python scripts for FPGA validation.
• Debug device and board issues; diagnose root causes in validation labs.
• Maintain revision control and collaborate across hardware teams.

Skills

FPGA design

Verilog/SystemVerilog

VHDL

Vivado

Synplify

Python scripting

C tests for FPGA

Timing analysis

Device/board debug

SVN version control

Tools

Synplify

Vivado

Xilinx FPGAs

Job description

HCL Technologies Limited in Belgium seeks a Senior Design Lead with 8–10 years of FPGA design and validation experience to drive complex FPGA projects from RTL to bit files and electrical validation. You will optimize timing constraints, address clock domain crossings, and collaborate with design teams while using Vivado and Synplify, Verilog/SystemVerilog, and Python for test development.

The role requires hands-on bench validation, debugging at device and board level, and experience with SVN