FPGA Validation Design Engineer

Qplox engineering; Vlaams-Brabant; Hybrid; EUR 50.000 - 84.000; Teilzeit

Zusammenfassung

Qplox engineering is seeking an FPGA/ASIC verification engineer to adapt RTL for FPGA integration and manage full verification flows. You will run FPGA development, perform synthesis, place-and-route, and analyze timing to achieve closure. The role requires hands-on debugging on hardware and experience with device and CPU verification.

The position is hybrid in Belgium (Vlaams-Brabant) with onsite and remote days, starting ASAP for a 3-month project.

Qualifikationen

• 5+ years in semiconductor FPGA design or verification.
• Strong SystemVerilog and UVM knowledge.
• Experience in device and CPU verification.
• Hands-on RTL, FPGA implementation and timing analysis.

Aufgaben

• Adapt and modify ASIC RTL for FPGA integration.
• Set up and execute FPGA development and verification flows.
• Perform FPGA database verification, synthesis, and place-and-route.
• Analyse timing reports, update constraints, and achieve timing closure.
• Debug FPGA bitstreams on hardware boards.
• Perform device- and CPU-level design verification.

Kenntnisse

SystemVerilog

UVM

RTL

FPGA implementation

timing analysis

hardware debugging

device verification

CPU verification

Jobbeschreibung

Key Responsibilities

• Adapt and modify ASIC RTL for FPGA integration.
• Set up and execute FPGA development and verification flows.
• Perform FPGA database verification, synthesis, and place-and-route.
• Analyse timing reports, update constraints, and achieve timing closure.
• Debug FPGA bitstreams on hardware boards.
• Perform device- and CPU-level design verification.

Required Skills

• 5+ years of relevant semiconductor, FPGA, or design verification experience.
• Strong knowledge of SystemVerilog and UVM.
• Experience in device-level and CPU verification.
• Hands-on experience with RTL, FPGA implementation, timing analysis, and hardware debugging.

Start Date: ASAP

Project Duration: 3 months

Working Arrangement: Hybrid – 3 days onsite, 2 days remote (flexibility possible after induction)