Senior FPGA/ASIC RTL Design Engineer: High-Performance Silicon

AMD; Elsene; On-site; EUR 90,000 - 140,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices, Inc. in Belgium is seeking a Senior Silicon Design Engineer to work on next-gen FPGA and Adaptive SoC platforms. You will design, validate, and optimize digital hardware, contributing across hardware and software domains.

The role requires strong RTL design skills, VHDL/Verilog/SystemVerilog, and collaboration with cross-functional teams to deliver high-performance silicon solutions. Mentoring junior engineers is encouraged.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Electronics and Communication Engineering, VLSI, or related field.
• 5-10 years of design experience in FPGA/ASIC development.
• Experience with RTL design using VHDL/Verilog/SystemVerilog.
• Strong problem-solving and debugging skills.
• Excellent collaboration across cross-disciplinary teams.

Responsibilities

• Design, develop, integrate, and validate digital hardware for FPGA and Adaptive SoC.
• Develop RTL using VHDL/Verilog/SystemVerilog with performance goals.
• Support FPGA implementation, synthesis, PnR, timing closure.
• Collaborate with hardware-software teams to optimize solutions.
• Create automation and regression tests for validation.

Skills

Digital design fundamentals

RTL design experience

Python scripting

Debugging skills

Independent ownership

Education

Bachelor's or Master's in ECE/VLSI

Tools

VHDL/Verilog/SystemVerilog

FPGA toolchain (Vivado)

Scripting (Bash/Tcl)

Job description

Advanced Micro Devices, Inc. in Belgium is seeking a Senior Silicon Design Engineer to work on next-gen FPGA and Adaptive SoC platforms. You will design, validate, and optimize digital hardware, contributing across hardware and software domains.

The role requires strong RTL design skills, VHDL/Verilog/SystemVerilog, and collaboration with cross-functional teams to deliver high-performance silicon solutions. Mentoring junior engineers is encouraged.