Hybrid FPGA Validation Engineer - Timing & Verification

Qplox engineering; Vlaams-Brabant; Ibrido; EUR 50.000 - 84.000; Part-time

Descrizione del lavoro

Qplox engineering is seeking an FPGA/ASIC verification engineer to adapt RTL for FPGA integration and manage full verification flows. You will run FPGA development, perform synthesis, place-and-route, and analyze timing to achieve closure. The role requires hands-on debugging on hardware and experience with device and CPU verification.

The position is hybrid in Belgium (Vlaams-Brabant) with onsite and remote days, starting ASAP for a 3-month project.

Competenze

• 5+ years in semiconductor FPGA design or verification.
• Strong SystemVerilog and UVM knowledge.
• Experience in device and CPU verification.
• Hands-on RTL, FPGA implementation and timing analysis.

Mansioni

• Adapt and modify ASIC RTL for FPGA integration.
• Set up and execute FPGA development and verification flows.
• Perform FPGA database verification, synthesis, and place-and-route.
• Analyse timing reports, update constraints, and achieve timing closure.
• Debug FPGA bitstreams on hardware boards.
• Perform device- and CPU-level design verification.

Conoscenze

SystemVerilog

UVM

RTL

FPGA implementation

timing analysis

hardware debugging

device verification

CPU verification

Descrizione del lavoro

Qplox engineering is seeking an FPGA/ASIC verification engineer to adapt RTL for FPGA integration and manage full verification flows. You will run FPGA development, perform synthesis, place-and-route, and analyze timing to achieve closure. The role requires hands-on debugging on hardware and experience with device and CPU verification.

The position is hybrid in Belgium (Vlaams-Brabant) with onsite and remote days, starting ASAP for a 3-month project.