Senior RTL Design Architect (Verilog/SystemVerilog)

Vivid Resourcing Ltd; Vlaams-Brabant; On-site; EUR 70,000 - 95,000; Full time

Benefits offered by this job

Salary commensurate with experience

Job summary

Vivid Resourcing Ltd seeks a Senior Digital Design Engineer to lead digital hardware development from architecture through RTL implementation. You will translate system requirements into robust digital designs, owning blocks and collaborating with verification and systems teams.

The role involves hands-on RTL coding in Verilog/SystemVerilog and mentoring junior engineers, with a focus on delivering high-quality digital solutions across ASIC/FPGA/SoC contexts.

Qualifications

• Degree in Electrical, Electronics or Computer Engineering.
• Several years of professional experience in digital hardware design and RTL development.
• Strong experience with Verilog and SystemVerilog.

Responsibilities

• Lead the design and development of complex digital hardware from specification through implementation.
• Develop high-quality, synthesizable RTL using Verilog and/or SystemVerilog.
• Translate requirements into efficient digital designs and own design blocks.
• Collaborate with verification and systems teams to define verification strategies.
• Support simulation, synthesis, timing analysis, debugging and hardware validation.

Skills

Digital design

RTL development

Verilog

SystemVerilog

ASIC

FPGA

SoC development

Mentoring

Education

Electrical/ Electronics/ Computer Engineering degree

Tools

Simulation tools

Synthesis tools

Timing analysis tools

Job description

Vivid Resourcing Ltd seeks a Senior Digital Design Engineer to lead digital hardware development from architecture through RTL implementation. You will translate system requirements into robust digital designs, owning blocks and collaborating with verification and systems teams.

The role involves hands-on RTL coding in Verilog/SystemVerilog and mentoring junior engineers, with a focus on delivering high-quality digital solutions across ASIC/FPGA/SoC contexts.