Senior Digital Back-End & DFT Engineer: PPA Focus

Jobtailor

Vlaams-Brabant

Sur place

EUR 75 000 - 115 000

Plein temps

14 jours+

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Résumé du poste

Jobtailor in Belgium seeks a senior digital backend layout engineer to own the back-end layout of a mixed-signal IC, from RTL to GDSII, using Cadence tools. You will drive DFT strategy and collaborate with design teams to optimize layouts for performance, power, and area, and you will verify layouts with Calibre/ICV.

Strong scripting in TCL/Perl and fluent English required; five+ years of industry experience.

Qualifications

Education: Bachelor’s or Master’s degree in Electrical Engineering (EE) or related field.
Minimum of 5 years hands-on experience in digital back-end layout/physical design.
Proven track record in taking RTL to GDSII.
Solid understanding of layout design principles and advanced process nodes.
Proficiency with Cadence digital layout tools.
Experience with physical verification tools such as Calibre or ICV.
Familiarity with scripting languages (TCL, Perl).
Strong analytical problem-solving, collaboration, and English fluency.

Responsabilités

Take ownership of the digital back-end layout design.
Design and implement the digital layout for a mixed-signal IC.
Execute the physical design using Cadence tools and verify the layout with advanced physical verification tools.
Partner with the design team to optimize physical layouts for performance, power, and area (PPA).
Provide immediate, actionable feedback to optimize design flows and physical implementation pipelines.
Drive Design for Test (DFT) insertion, architecture, and strategy to ensure high test coverage.