Staff Digital Design Engineer

microTECH Global LTD; Heverlee; À distance; EUR 70 000 - 95 000; Plein temps

Résumé du poste

microTECH Global Limited in Leuven, Belgium is seeking a Staff Digital Design Engineer to design advanced digital building blocks including power management and low-power applications. The role focuses on robust RTL development and collaborative design across teams.

You will specify, lint, synthesize, and optimize timing and power, working with analog, verification and physical design teams to close designs on timing and power. 4+ years RTL experience and strong English are required.

Qualifications

• BS or MS in Electrical Engineering, microelectronics preferred.
• 4+ years' industry RTL development experience.
• Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog.
• Knowledge of UVM testbench development.
• Strong communication and presentation skills in English.

Responsabilités

• Design micro-architecture specifications and design documentation.
• RTL development using VHDL or Verilog/SystemVerilog following guidelines.
• Lint, CDC, Synthesis, and Power Optimization.
• Soft and hard IP identification, selection and integration.
• Timing and power constraints development.
• Collaborate with analog, verification and physical design teams to meet timing and power goals.

Connaissances

RTL development

VHDL

Verilog/SystemVerilog

UVM testbench

English communication

Formation

B.S./M.S. in Electrical Engineering

Outils

Synthesis

Place-and-Route

UVM

Description du poste

Job Title: Staff Digital Design Engineer

Location: Leuven, Belgium

Job Type: Permanent

Salary: DOE

Role Overview

Design advanced digital building blocks for various applications, incl. but not limited to power management, low-power & low-voltage applications.

Key Responsibilities

• Micro-architecture specification development and design documentation
• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debug
• Collaboration with physical design team to close the design on timing and power

Experience Required

• B.S. or M.S. degree in Electrical Engineering, microelectronics preferred.
• 4+ yrs' industry experience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/System Verilog
• Knowledge of UVM Testbench development
• Strong communication and presentation skills in English

Desirable

• Knowledge of mixed signal concepts
• Hands-on experience with synthesis and/or place-and-route
• Able to work in a team
• Good problem solving skills and being able to implement solutions autonomously
• Understanding of Dutch language