FE RTL Designer / SoC integration

Vertical Compute; Vlaams-Brabant; Sur place; EUR 65 000 - 90 000; Plein temps

Résumé du poste

Vertical Compute is seeking a Front-End RTL Designer to contribute to building our 3D-integrated chiplets and AI accelerator platforms. You will lead top-level SoC/chiplet integration, collaborating with verification and physical design teams to achieve target PPA metrics.

You should have a solid background in front-end RTL design (SystemVerilog/Verilog) and experience integrating IP blocks into unified silicon architectures, working in a fast-paced, collaborative hardware environment.

Qualifications

• Solid background in front-end RTL design and top-level SoC/chiplet integration.
• Degree in Electrical Engineering, Computer Engineering, Microelectronics, or related field.
• Strong SystemVerilog/Verilog skills and IP integration experience.
• Excellent collaboration and communication in a fast-paced hardware environment.

Responsabilités

• Lead top-level SoC and chiplet integration with internal and external IPs.
• Integrate VIM technology with compute engines to optimize throughput.
• Work with verification teams to build environments and debug RTL issues.
• Collaborate with physical design to meet PPA targets and timing closures.

Connaissances

Front-end RTL design

SoC/chiplet integration

IP integration

SystemVerilog/Verilog

Collaboration & communication

English language

Formation

Electrical/Computer Engineering or related field

Description du poste

About Us:

AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.

Why Now:

After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.

About the role:

We are looking for a Front-End RTL Designer to contribute to building our Vertical Compute's 3D-integrated chiplets. In this role, you will focus on top-level integration and integrating all IPs to build the AI accelerator that will demonstrate the full potential of our Vertical Integrated Memory (VIM™) technology. You will handle full SoC integration, working in close collaboration with verification and physical design teams to ensure the targeted Power, Performance, and Area (PPA) of the product.

Key Responsibilities:

• Lead top-level SoC and chiplet integration, incorporating all internal and third-party IPs to build high-performance AI accelerators.
• Integrate proprietary Vertical Integrated Memory (VIM™) technology with compute engines to maximize throughput and bandwidth efficiency.
• Partner closely with functional verification teams to build verification environments, debug RTL issues, and ensure robust design coverage.
• Collaborate with physical design teams to optimize Power, Performance, and Area (PPA), supporting synthesis, timing closure, and floorplanning.

About the team:

This role is part of the Hardware (HW) team, reporting directly to the HW Manager. You will join a collaborative and innovative team dedicated to delivering cutting-edge AI accelerator solutions and pushing the boundaries of memory and compute integration.

About who you are:

• Solid background and experience in front-end RTL design and top-level SoC/chiplet integration.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
• Strong hard skills in RTL languages (SystemVerilog/Verilog), IP integration, and working closely with verification and physical design teams to optimize PPA (Power, Performance, Area).
• Strong communication and collaborative problem-solving skills in a fast-paced environment.
• Fluency in English with effective written and verbal communication skills.

Role context:

This role exists to bridge high-level system architectural specifications and physical silicon implementation within complex microelectronics organizations. Situated between logic verification engineers, physical design specialists, and third-party IP vendors, front-end designers convert architectural concepts into functional register-transfer level code. The position ensures structured integration of diverse intellectual property blocks into unified system-on-chip architectures. Engineers in this function maintain technical focus on meeting power, performance, and area constraints prior to physical fabrication and hardware deployment.

Quantum ecosystem relevance:

Front-end RTL design serves as enabling infrastructure for quantum technologies by providing custom digital control logic and specialized signal processing hardware. Advanced quantum systems rely on low-latency electronic controllers, custom co-processors, and integrated microarchitectures to execute quantum control sequences and error correction protocols. While primarily rooted in semiconductor design, engineers operating at this level establish foundational hardware integration frameworks essential for scalable classical-quantum hybrid interfaces and advanced computing accelerators across deep-technology environments.

Capability signals:

• Expertise in front-end register-transfer level design and system-on-chip integration methods
• Ability to integrate internal and external intellectual property blocks into custom silicon architectures
• Proficiency in collaborating with verification engineering teams for design coverage and debugging
• Experience optimizing target power, performance, and area metrics alongside physical design engineers
• Skill in bridging hardware architecture specifications with downstream microelectronics implementation workflows