Lead RTL Verification Engineer for AI Chiplets

Vertical Compute SRL; Leuven; Hybride; EUR 70 000 - 110 000; Plein temps

Résumé du poste

Vertical Compute is seeking an RTL Verification Engineer to lead verification of our 3D-integrated chiplets, focusing on top-level validation of the chiplets and their tight coupling with the VIM memory technology. You will work with Front-End RTL Design, System Architecture and Software teams to ensure tape-out readiness.

The role requires strong SystemVerilog/UVM expertise, a track record in ASIC/SoC verification, and excellent collaboration and English communication.

Qualifications

• Proven track record in ASIC/SoC functional verification, including top-level verification of complex multi-IP designs or AI compute accelerators.
• Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related discipline.
• Strong expertise in SystemVerilog, UVM, assertion-based verification, and coverage-driven verification for complex hardware architectures.
• Strong collaborative mindset and problem-solving skills to work effectively with cross-functional FE Design, System, and SW teams.
• Fluency in English with excellent written and verbal communication skills.

Responsabilités

• Lead top-level functional verification for our next-generation AI compute chiplet, ensuring complete protocol compliance and robust multi-die integration.
• Architect, deploy, and maintain advanced UVM/SystemVerilog testbenches, assertions, and constrained-random test plans for memory and compute subsystems.
• Drive coverage-driven verification, target debug, and root-cause analysis across complex hardware-software boundary scenarios.
• Collaborate closely with Front-End RTL Design, System Architecture, and Software/Compiler teams to achieve full tape-out readiness and post-silicon validation.
• Benchmark and analyze system-level performance to demonstrate the throughput, bandwidth, and energy efficiency of Vertical Compute's VIM™ technology.

Connaissances

ASIC/SoC verification

SystemVerilog

UVM

Constrained-random testing

HW-SW collaboration

Formation

Electrical/Computer Engineering or Microelectronics (B.S./M.S./Ph.D.)

Outils

SystemVerilog

UVM

Assertions

Description du poste

Vertical Compute is seeking an RTL Verification Engineer to lead verification of our 3D-integrated chiplets, focusing on top-level validation of the chiplets and their tight coupling with the VIM memory technology. You will work with Front-End RTL Design, System Architecture and Software teams to ensure tape-out readiness.

The role requires strong SystemVerilog/UVM expertise, a track record in ASIC/SoC verification, and excellent collaboration and English communication.